[PATCH v3 0/2] spi: omap2-mcspi: add FIFO buffer support

[Illia Smyrnov]

These patches introduce FIFO support for TI OMAP4/OMAP5 MCSPI controller.
Using FIFO unload the DMA and improve data throughput. On Blaze (OMAP 4460) 
ethernet throughput with MTU 1500 was increased:
* for TX from 6.9476 Mbps (FIFO disabled) to 8.1046 Mbps (FIFO enabled),
* for RX from 6.5120 Mbps (FIFO disabled) to 7.6091 Mbps (FIFO enabled).

The FIFO sanity test on OMAP5 Panda board also has been done. 

The FIFO is enabled for SPI transfers in DMA mode. The largest possible FIFO
buffer size will be calculated and set up. The FIFO won't be used for the SPI
transfers in DMA mode if: calculated FIFO buffer size is less then 2 bytes or
the FIFO buffer size isn't multiple of the SPI word length.

The MCSPI FIFO constraints are:
* FIFO depth size defined as a multiple of the SPI word length;
* transfer's data size is a multiple of FIFO depth;
* transfer's words count less or equal 65535.

Also FIFO buffer with 1 byte size is insignificant, so driver will setup FIFO if
calculated size is within the 2 to 64 bytes range.

--------------------
v3:
* FIFO enadled for all SPI transfers in DMA mode.

--------------------
v2:
* driver calculate and setup optimal FIFO size for each SPI transfer;
* "ti,spi-fifo-enabled" parameter in MCSPI DT node to enable FIFO;
* no FIFO settings in SPI slaves nodes in DT;
* Matthias Brugger patch was excluded from patch set.

Illia Smyrnov (2):
  spi: omap2-mcspi: Move bytes per word calculation to the function
  spi: omap2-mcspi: Add FIFO buffer support

 drivers/spi/spi-omap2-mcspi.c |  166 +++++++++++++++++++++++++++++++++++------
 1 files changed, 143 insertions(+), 23 deletions(-)

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