Re: [PATCH 6/6] x86/PCI: quirk Thunderbolt PCI-to-PCI bridges

[Bjorn Helgaas]

On Wed, Jun 26, 2013 at 4:31 PM, Yinghai Lu <yinghai@xxxxxxxxxx> wrote:
> On Wed, Jun 26, 2013 at 3:26 PM, Yinghai Lu <yinghai@xxxxxxxxxx> wrote:
>> On Wed, Jun 26, 2013 at 3:18 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote:
>>> On Tue, Jun 25, 2013 at 10:22 AM, Mika Westerberg
>>> <mika.westerberg@xxxxxxxxxxxxxxx> wrote:
>>>> Thunderbolt PCI-to-PCI bridges typically use BIOS "assisted" enumeration.
>>>> This means that the BIOS will allocate bridge resources based on some
>>>> assumptions of a maximum Thunderbolt chain. It also disables native PCIe
>>>> hotplug of the root port where the Thunderbolt host router is connected.
> ...
> During acpi hotplug, firmare could do extra help for us like assign
> some resources to pci device bars, so it is NOT "boot-time".

Really?  How can firmware assign BARs at hotplug-time?  I mean,
obviously firmware *can* write things to the BARs before giving the
device to the OS, but how would it know what to write?  I assume the
OS owns the address space, and it can change the upstream bridge
windows or the BARs of another device on the bus at any time, subject
to the OS's own issues as far as quiescing or unbinding drivers, etc.,
but without coordinating with the BIOS.

Bjorn
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