Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys partand Exynos part

[Jingoo Han]

On Thursday, July 11, 2013 5:55 PM, Kishon Vijay Abraham I wrote:
> On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote:
> > Exynos PCIe IP consists of Synopsys specific part and Exynos
> > specific part. Only core block is a Synopsys designware part;
> > other parts are Exynos specific.
> > Also, the Synopsys designware part can be shared with other
> > platforms; thus, it can be split two parts such as Synopsys
> > designware part and Exynos specific part.
> >
> > Signed-off-by: Jingoo Han <jg1.han@xxxxxxxxxxx>
> > Cc: Pratyush Anand <pratyush.anand@xxxxxx>
> > Cc: Mohit KUMAR <Mohit.KUMAR@xxxxxx>
> > ---
> .
> .
> <snip>
> .
> .
> > +
> > +/* Exynos PCIe driver does not allow module unload */
> 
> Just curious, why is this restriction?

CC'ed Thierry Reding,

Hi Kishon,

That's a good question.

Now, we don't have the solution to "be able to load and unload
the PCI host driver in a loop definitely without crashing or exposing
any races  or leaks", as Arnd Bergmann said.
Please refer to the following thread in mailing-list.
(http://archive.arm.linux.org.uk/lurker/message/20130614.123849.4ff363c5.pl.html)

Thus, Exynos PCIe did not support unloading module.
(http://archive.arm.linux.org.uk/lurker/message/20130614.125338.7d2bbf62.pl.html)

Best regards,
Jingoo Han


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