Re: [PATCH] perf, x86: Add Silvermont (22nm Atom) support

[Peter Zijlstra]

On Thu, Jul 18, 2013 at 01:36:07PM +0800, Yan, Zheng wrote:
> From: "Yan, Zheng" <zheng.z.yan@xxxxxxxxx>
> 
> Compare to old atom, Silvermont has offcore and has more events
> that support PEBS.
> 
> Silvermont has two offcore response configuration MSRs, but the
> event code for OFFCORE_RSP_1 is 0x02b7. To avoid complicating
> intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to define offcore
> MSRs. So intel_fixup_er() can find the code for OFFCORE_RSP_1
> by x86_pmu.extra_regs[1].event.

Please split this in two patches; one reworking the OFFCORE_RSP stuff;
one adding slm support.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/