Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

[Vince Weaver]

On Sat, 20 Apr 2013, Andi Kleen wrote:

> From: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> 
> Haswell has two additional LBR from flags for TSX: intx and abort, implemented
> as a new v4 version of the LBR format.
> 
> Handle those in and adjust the sign extension code to still correctly extend.
> The flags are exported similarly in the LBR record to the existing misprediction
> flag

I'm trying to update the perf_event_open() manpage for the new changes 
that were in Linux 3.11 and am having trouble getting info on exactly
what these new fields mean.

> +	PERF_SAMPLE_BRANCH_ABORT_TX	= 1U << 7, /* transaction aborts */
> +	PERF_SAMPLE_BRANCH_IN_TX	= 1U << 8, /* in transaction */
> +	PERF_SAMPLE_BRANCH_NO_TX	= 1U << 9, /* not in transaction */

so if you specify these flags in branch_sample_type, what information
appears in the branch record?  

If you get an abort, what address appears in the record?

What does it mean in regards to a branch entry to be or not be in a 
transaction?  

If you set "in transaction" does that then only record branches that are 
in transactions?  What happens if you set both in transaction and not in?

Is there some sort of document from intel you can link to that describes 
all of this?

Thanks,

Vince

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