Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

[Andi Kleen]

On Tue, Sep 03, 2013 at 05:14:51PM -0400, Vince Weaver wrote:
> On Tue, 3 Sep 2013, Andi Kleen wrote:
> 
> > > > +	PERF_SAMPLE_BRANCH_ABORT_TX	= 1U << 7, /* transaction aborts */
> > > > +	PERF_SAMPLE_BRANCH_IN_TX	= 1U << 8, /* in transaction */
> > > > +	PERF_SAMPLE_BRANCH_NO_TX	= 1U << 9, /* not in transaction */
> > > 
> > > so if you specify these flags in branch_sample_type, what information
> > > appears in the branch record?  
> > 
> > This is just a filter, so when set branches that do not satisfy
> > the filter are not reported.
> 
> Is the implementation a direct mapping to the LBR documentation or has it 
> been generic so non-Intel architectures can use it?

It's not a direct mapping (no_tx doesn't exist in the hardware)
If other architectures have similar capabilities they can likely use it.

> 
> > The patches to export the new fields haven't been merged yet.
> 
> What does this mean?  The above values are exported as part of 
>   include/uapi/linux/perf_event.h
> Do they not work yet?

You can filter on the fields, but you can't see them outside
the kernel driver yet.  The patch to see them is still pending.
> 
> > >  What happens if you set both in transaction and not in?
> > 
> > Then you get all branches.
> 
> so what happens if you set neither "PERF_SAMPLE_BRANCH_IN_TX" nor
> "PERF_SAMPLE_BRANCH_NO_TX"?  Logically you'd get no branches at all,
> but that can't be true as all code prior to 3.11 didn't set those values.

Then you get all branches too

(that's how all the other filters work too)

-Andi

-- 
ak@xxxxxxxxxxxxxxx -- Speaking for myself only.
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