Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver

[Kishon Vijay Abraham I]

On Monday 04 November 2013 05:56 PM, Tomasz Figa wrote:
> Hi Kishon,
>
> On Monday 04 of November 2013 12:24:42 Kishon Vijay Abraham I wrote:
> > Hi Vivek,
> >
> > On Thursday 31 October 2013 01:15 PM, Vivek Gautam wrote:
> > > Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
> > > The new driver uses the generic PHY framework and will interact
> > > with DWC3 controller present on Exynos5 series of SoCs.
> >
> > In Exynos, you have a single IP that supports both USB3 and USB2 PHY
> > right? I think that needs to be mentioned here.
>
> Nope. There are two separate, different IPs.

Alright. Thanks for the clarification.

Cheers
Kishon

> > Do you have separate registers that should be used for
> > initializing/powerin_on/powering_off etc.. for usb2 phy and usb3 phy? If
> > so, then you should model this driver as a single driver that supports
> > two PHYs similar to what Sylwester has done before?
>
> Sylwester's MIPI PHY uses such model because it has a single register
> that controls both PHYs.
>
> Best regards,
> Tomasz

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