perf events: how to implement TLB misses as SW event ?

[christophe leroy]

Today in the perfevents subsystem it looks like DTLB/ITLB misses are 
implemented as HW counter only.
On some processors, like PowerPC 8xx, there is no counter for that. 
However DTLB/ITLB misses are handled as exceptions via software, so we 
have an opportunity to implement a SW counter for that.
What's the easiest/best way to implement it ?

Christophe
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