Re: TSC Problems (warp between CPUs)

[Alex]

On 2013-12-29 01:35, One Thousand Gnomes wrote:
> > not guaranteed to be precise. For example a SMI (System Management
> > Interrupt) could interrupt the software flow that is attempting to 
> > write
> > the time-stamp counter immediately prior to the WRMSR. This could 
> > mean
> > the value written to the TSC could vary by thousands to millions of
> > clocks.
>
> Yes SMI is a disaster area for any real time activity (and many other
> things ;) ), but many systems actually make little use of it, 
> especially
> once the USB is owned by the OS.
>
> For synchronization you can retry the sync if it isn't within an
> acceptable range. The odds of getting an SMI mid sync setup should be
> very very low, so the odds of repeating the failure several times 
> should
> be negligible and after a few tries you could give up and assume the
> hardware is buggered then fall back to HPET.

Hi Alan,

The sync retry sounds like an interesting strategy but is outside my 
knowledge
scope as a regular end user (I do have a reasonable understanding of C 
and can patch+
recompile) but I lack the architecture knowledge to implement a patch 
to do this.

Any suggestions?

--
Kind Regards,
Alex.

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/