Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver

[Vivek Gautam]

Hi Kishon,


[...]

>>>>>>>>>>>> Right.
>>>>>>>>>>>>
>>>>>>>>>>>> While 3.0 block(PIPE3) can be used for Super Speed, 2.0
>>>>>>>>>>>> block(UTMI+)
>>>>>>>>>>>> can be used for High speed.
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> It should then come under *single IP muliple PHY* category similar
>>>>>>>>>>> to what
>>>>>>>>>>> Sylwester has done.

[...]

>>
>> The idea is to model the driver as close to the hardware though I understand
>> there won't be any advantages w.r.t power or performance. maybe in later
>> versions of the IP we'll have separate bits to control usb3 and usb2.
>
> Ok, i will prepare the next patchset for separating out the possible
> code based on
> the UTMI+ or PIPE3 phys. Though when experimenting with the PHY
> settings i can see
> there's little of such code  :-)
>
>>
>> I think for power control we should have both usb3 and usb2 power-on callback
>> calling a single function that controls the power bit.
> Right. I will do that.

Have posted the next version of patch with functionality to support
multiple PHYs as suggested.
Please review the same.
Thanks !!


-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
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