Re: x86: Inconsistent xAPIC synchronization in arch_irq_work_raise?
From: Huang Ying
Date: Tue Jan 21 2014 - 18:20:33 EST
On Tue, 2014-01-21 at 15:51 +0100, Peter Zijlstra wrote:
> On Tue, Jan 21, 2014 at 03:01:13PM +0100, Peter Zijlstra wrote:
> > On Tue, Jan 21, 2014 at 02:02:06PM +0100, Jan Kiszka wrote:
> > > Hi all,
> > >
> > > while trying to plug a race in the CPU hotplug code on xAPIC systems, I
> > > was analyzing IPI transmission patterns. The handlers in
> > > arch/x86/include/asm/ipi.h first wait for ICR, then send. In contrast,
> > > arch_irq_work_raise sends the self-IPI directly and then waits. This
> > > looks inconsistent. Is it intended?
> > >
> > > BTW, the races are in wakeup_secondary_cpu_via_init and
> > > wakeup_secondary_cpu_via_nmi (lacking IRQ disable around ICR accesses).
> > > There we also send first, then wait for completion. But I guess that is
> > > due to the code originally only being used during boot. Will send fixes
> > > for those once the sync pattern is clear to me.
> > Could be I had no clue what I was doing and copy/pasted the code until
> > it compiled and ran.
> > In fact, I've got no clue what an ICR is.
> I dug about a bit, I borrowed that code from:
> Huang Ying, can you explain to Jan why you do the wait afterwards?
I borrow the code from the original MCE report event code.
Andi, could you help us to explain it?
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