Re: [BISECTED] OMAP: DSS: clk rate mismatch

[Tomi Valkeinen]

On 2014-01-28 20:17, Ivaylo Dimitrov wrote:
> 
> 
> On 28.01.2014 10:48, Tomi Valkeinen wrote:
> 
>> I made a somewhat hacky quickfix for beagle. Applying that and the
>> clk-divider from the link above makes things work for me. However, as I
>> said, the issue with n900 might be different, but it'd be interesting to
>> hear if it has any effect.
>>
>>   Tomi
>>
> 
> Applying those 2 patches doesn't help, still get exactly the same warning.
> 
> Find attached my clk_summary (with my hacky patch applied, otherwise I
> cannot boot the device)

Can you try this one:

From e511789f7be00beeeee0712910c60a57c51b2705 Mon Sep 17 00:00:00 2001
From: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
Date: Wed, 29 Jan 2014 13:28:53 +0200
Subject: [PATCH] clkoutx2 fix

---
 arch/arm/mach-omap2/cclock3xxx_data.c |  7 +++++++
 arch/arm/mach-omap2/dpll3xxx.c        | 20 ++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 3b05aea56d1f..49247701a56c 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -428,12 +428,19 @@ static const char *dpll4_m5x2_ck_parent_names[] = {
 	"dpll4_m5_ck",
 };
 
+int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
+					unsigned long parent_rate);
+long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long target_rate,
+		unsigned long *parent_rate);
+
 static const struct clk_ops dpll4_m5x2_ck_ops = {
 	.init		= &omap2_init_clk_clkdm,
 	.enable		= &omap2_dflt_clk_enable,
 	.disable	= &omap2_dflt_clk_disable,
 	.is_enabled	= &omap2_dflt_clk_is_enabled,
+	.set_rate	= &omap3_clkoutx2_set_rate,
 	.recalc_rate	= &omap3_clkoutx2_recalc,
+	.round_rate	= &omap3_clkoutx2_round_rate,
 };
 
 static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3a0296cfcace..794665fe234b 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -669,6 +669,26 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 	return rate;
 }
 
+int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
+					unsigned long parent_rate)
+{
+	return 0;
+}
+
+long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
+		unsigned long *prate)
+{
+	if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+		unsigned long best_parent;
+
+		best_parent = (rate / 2);
+		*prate = __clk_round_rate(__clk_get_parent(hw->clk),
+				best_parent);
+	}
+
+	return *prate * 2;
+}
+
 /* OMAP3/4 non-CORE DPLL clkops */
 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
 	.allow_idle	= omap3_dpll_allow_idle,
-- 
1.8.3.2

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