On Wed, 29 Jan 2014 14:53:32 -0300, Ezequiel Garcia <ezequiel.garcia@xxxxxxxxxxxxxxxxxx> wrote:On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:Sorry, binding review has become a huge undertaking.nand-ecc-level property statically defines NAND chip's ECC requirements.Hm.. when was this proposal agreed? It seems I've missed the
Signed-off-by: Boris BREZILLON <b.brezillon.dev@xxxxxxxxx>
---
Documentation/devicetree/bindings/mtd/nand.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index 03855c8..0c962296 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -3,5 +3,8 @@
- nand-ecc-mode : String, operation mode of the NAND ecc mode.
Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
"soft_bch".
+- nand-ecc-level : Two cells property defining the ECC level requirements.
+ The first cell represent the strength and the second cell the ECC block size.
+ E.g. : nand-ecc-level = <4 512>; /* 4 bits / 512 bytes */
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
discussion...
FWIW, we've already proposed an equivalent one, but it received no
feedback from the devicetree maintainers:
http://comments.gmane.org/gmane.linux.drivers.devicetree/58764I'm okay with either, but the above binding is indeed more readable.
Maybe we can discuss about it now?
nand-ecc-strength : integer ECC required strength.
nand-ecc-size : integer step size associated to the ECC strength.
g.