[PATCH] [RFC] clk:mvebu: make clock-output-names mandatory

[Gregory CLEMENT]

Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxxxxxxxxx>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |  7 ++--
 arch/arm/boot/dts/armada-370.dtsi                  |  1 +
 drivers/clk/mvebu/common.c                         | 38 +++++++++++++++-------
 3 files changed, 31 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 307a503c5db8..4f2e3953b6a6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -40,16 +40,15 @@ Required properties:
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
 - reg : shall be the register address of the Sample-At-Reset (SAR) register
 - #clock-cells : from common clock binding; shall be set to 1
-
-Optional properties:
-- clock-output-names : from common clock binding; allows overwrite default clock
-	output names ("tclk", "cpuclk", "l2clk", "ddrclk")
+- clock-output-names : from common clock binding; should be the clock
+	output names given above
 
 Example:
 
 core_clk: core-clocks@d0214 {
 	compatible = "marvell,dove-core-clock";
 	reg = <0xd0214 0x4>;
+	clock-output-names = "tclk", "cpuclk", "l2clk", "ddrclk";
 	#clock-cells = <1>;
 };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index af1f11e9e5a0..0d5853d05bd6 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -196,6 +196,7 @@
 			coreclk: mvebu-sar@18230 {
 				compatible = "marvell,armada-370-core-clock";
 				reg = <0x18230 0x08>;
+				clock-output-names = "tclk", "cpuclk", "nbclk", "hclk", "dramclk";
 				#clock-cells = <1>;
 			};
 
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 25ceccf939ad..5e7c9274e4d3 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -51,16 +51,21 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 	}
 
 	/* Register TCLK */
-	of_property_read_string_index(np, "clock-output-names", 0,
-				      &tclk_name);
+	if (of_property_read_string_index(np, "clock-output-names", 0,
+						&tclk_name))
+		pr_err("%s[0]: clock-output-names is mandatory\n"
+			"\"%s\" will be used by default\n", np->name, tclk_name);
 	rate = desc->get_tclk_freq(base);
 	clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
 						   CLK_IS_ROOT, rate);
 	WARN_ON(IS_ERR(clk_data.clks[0]));
 
 	/* Register CPU clock */
-	of_property_read_string_index(np, "clock-output-names", 1,
-				      &cpuclk_name);
+	if (of_property_read_string_index(np, "clock-output-names", 1,
+						&cpuclk_name))
+		pr_err("%s[1]: clock-output-names is mandatory\n"
+			"\"%s\" will be used by default\n",
+			np->name, cpuclk_name);
 	rate = desc->get_cpu_freq(base);
 	clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
 						   CLK_IS_ROOT, rate);
@@ -71,8 +76,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 		const char *rclk_name = desc->ratios[n].name;
 		int mult, div;
 
-		of_property_read_string_index(np, "clock-output-names",
-					      2+n, &rclk_name);
+		if (of_property_read_string_index(np, "clock-output-names",
+							2+n, &rclk_name))
+			pr_err("%s[%d]:clock-output-names is mandatory\n"
+				"\"%s\" will be used by default\n",
+				np->name, 2+n, rclk_name);
 		desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
 		clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
 				       cpuclk_name, 0, mult, div);
@@ -119,19 +127,27 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
 				   const struct clk_gating_soc_desc *desc)
 {
 	struct clk_gating_ctrl *ctrl;
-	struct clk *clk;
 	void __iomem *base;
 	const char *default_parent = NULL;
 	int n;
+	struct of_phandle_args clkspec;
 
 	base = of_iomap(np, 0);
 	if (WARN_ON(!base))
 		return;
 
-	clk = of_clk_get(np, 0);
-	if (!IS_ERR(clk)) {
-		default_parent = __clk_get_name(clk);
-		clk_put(clk);
+	if (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0, &clkspec)) {
+		of_property_read_string_index(clkspec.np, "clock-output-names",
+					clkspec.args_count ? clkspec.args[0] : 0,
+					&default_parent);
+		if (WARN_ON(default_parent == NULL)) {
+			pr_err("%s: The clock-output-names of the parent clock is mandatory.\n"
+				"%s: As this proprety is missing, this parent will be ignored.\n"
+				"%s: The tclk clock will be used as parent clock\n",
+				np->name, np->name, np->name);
+			default_parent = "tclk";
+		}
+		of_node_put(clkspec.np);
 	}
 
 	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
-- 
1.8.1.2


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