Re: [PATCH v1 07/11] x86: perf: intel_pt: Intel PT PMU driver

[Alexander Shishkin]

Peter Zijlstra <peterz@xxxxxxxxxxxxx> writes:

> On Thu, Feb 06, 2014 at 12:50:30PM +0200, Alexander Shishkin wrote:
>> Add support for Intel Processor Trace (PT) to kernel's perf/itrace events.
>> PT is an extension of Intel Architecture that collects information about
>> software execuction such as control flow, execution modes and timings and
>> formats it into highly compressed binary packets. Even being compressed,
>> these packets are generated at hundreds of megabytes per second per core,
>> which makes it impractical to decode them on the fly in the kernel. Thus,
>> buffers containing this binary stream are zero-copy mapped to the debug
>> tools in userspace for subsequent decoding and analysis.
>> 
>> Signed-off-by: Alexander Shishkin <alexander.shishkin@xxxxxxxxxxxxxxx>
>> ---
>>  arch/x86/include/uapi/asm/msr-index.h     |  18 +
>>  arch/x86/kernel/cpu/Makefile              |   1 +
>>  arch/x86/kernel/cpu/intel_pt.h            | 127 ++++
>>  arch/x86/kernel/cpu/perf_event.c          |   4 +
>>  arch/x86/kernel/cpu/perf_event_intel.c    |  10 +
>>  arch/x86/kernel/cpu/perf_event_intel_pt.c | 991 ++++++++++++++++++++++++++++++
>>  6 files changed, 1151 insertions(+)
>>  create mode 100644 arch/x86/kernel/cpu/intel_pt.h
>>  create mode 100644 arch/x86/kernel/cpu/perf_event_intel_pt.c
>
> Andi said that when itrace is enabled the LBR is wrecked; this patch
> seems to fail to deal with that.

True, there needs to be a _safe() msr access before any configuration is
done, I have a fix for that, but let's first deal with the buffer
management.

Regards,
--
Alex
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