Re: [PATCH 08/19] perf c2c: Shared data analyser

[Andi Kleen]

> Heh.  I never thought about that.  And sure enough a quick test with
> mem-stores commented out produced the same results (minus the stores).
> 
> One would just have to 'figure' out what cacheline offsets are causing the
> HITMs.

Often that can be determined statically from the instruction (register-offset)

However keep in mind that there is some skid so the instruction may not
be correct.

-Andi

-- 
ak@xxxxxxxxxxxxxxx -- Speaking for myself only.
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