I don't think so - while it (as we now see) disallows certain thingsOn 03/17/2014 05:19 AM, George Dunlap wrote:On 17.03.14 at 17:55, "H. Peter Anvin" <hpa@xxxxxxxxx> wrote:
On Mon, Mar 17, 2014 at 3:33 AM, H. Peter Anvin <hpa@xxxxxxxxx> wrote:workaround for the legacy hypervisor versions.
No, the right thing is to unf*ck the Xen braindamage and use eagerfpu as a
The interface wasn't an accident. In the most common case you'll wantThe interface was a complete faceplant, because it caused failures.
to clear the bit anyway. In PV mode clearing it would require an extra
trip up into the hypervisor. So this saves one trip up into the
hypervisor on every context switch which involves an FPU, at the
expense of not being able to context-switch away when handling the
trap.
You're not infinitely unconstrained since you want to play in the same
sandbox as the native architecture, and if you want to have a hope of
avoiding these kinds of failures you really need to avoid making random
"improvements", certainly not without an explicit guest opt-in (the same
we do for the native CPU architecture when adding new features.)
So if this interface wasn't an accident it was active negligence and
incompetence.
inside the guest, back at the time when this was designed there was
no sign of any sort of allocation/scheduling being done inside the
#NM handler. And furthermore, a PV specification is by its nature
allowed to define deviations from real hardware behavior, or else it
wouldn't be needed in the first place.