[PATCH 3.13 043/149] ARC: Use correct PTAG register for icache flush

From: Greg Kroah-Hartman
Date: Thu Mar 20 2014 - 21:25:03 EST

3.13-stable review patch. If anyone has any objections, please let me know.


From: Vineet Gupta <vgupta@xxxxxxxxxxxx>

commit b053940df41808f0f27568eb36820d10a8a987f8 upstream.

This fixes a subtle issue with cache flush which could potentially cause
random userspace crashes because of stale icache lines.

This error crept in when consolidating the cache flush code

Fixes: bd12976c3664 (ARC: cacheflush refactor #3: Unify the {d,i}cache)
Signed-off-by: Vineet Gupta <vgupta@xxxxxxxxxxxx>
Cc: arc-linux-dev@xxxxxxxxxxxx
Signed-off-by: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

arch/arc/mm/cache_arc700.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -282,7 +282,7 @@ static inline void __cache_line_loop(uns
/* if V-P const for loop, PTAG can be written once outside loop */
if (full_page_op)
- write_aux_reg(ARC_REG_DC_PTAG, paddr);
+ write_aux_reg(aux_tag, paddr);

while (num_lines-- > 0) {
@@ -296,7 +296,7 @@ static inline void __cache_line_loop(uns
write_aux_reg(aux_cmd, vaddr);
vaddr += L1_CACHE_BYTES;
- write_aux_reg(aux, paddr);
+ write_aux_reg(aux_cmd, paddr);
paddr += L1_CACHE_BYTES;

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