Re: [PATCH] x86,mm: delay TLB flush after clearing accessed bit

[Linus Torvalds]

On Tue, Apr 1, 2014 at 9:11 AM, Rik van Riel <riel@xxxxxxxxxx> wrote:
>
> Memory pressure is not necessarily caused by the same process
> whose accessed bit we just cleared. Memory pressure may not
> even be caused by any process's virtual memory at all, but it
> could be caused by the page cache.

If we have that much memory pressure on the page cache without having
any memory pressure on the actual VM space, then the swap-out activity
will never be an issue anyway.

IOW, I think all these scenarios are made-up. I'd much rather go for
simpler implementation, and make things more complex only in the
presence of numbers. Of which we have none.

              Linus
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