Re: [PATCH 6/6] perf: Add dcacheline sort

[Stephane Eranian]

On Fri, May 16, 2014 at 5:59 PM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> On Fri, May 16, 2014 at 04:09:59PM +0200, Stephane Eranian wrote:
>> > +#define CACHE_LINESIZE       64
>> I had something similar to your patch here in my original series for
>> perf mem, but I never pushed it.
>> I think this is a useful feature to have.
>> However, I don't think you can hardcode the cache line size to 64.
>> This is generic
>> code. There may be architectures where the line size is different from 64.
>> So I think you should add an option to change the default line size or provide
>> an arch-specific definition.
>
> # cat /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
> 64
Excellent, then we should use that!
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