Re: [PATCH 6/6] perf: Add dcacheline sort

[Don Zickus]

On Mon, May 19, 2014 at 01:25:45PM +0200, Jiri Olsa wrote:
> On Fri, May 16, 2014 at 12:24:41PM -0400, Don Zickus wrote:
> > On Fri, May 16, 2014 at 06:02:43PM +0200, Stephane Eranian wrote:
> > > On Fri, May 16, 2014 at 5:59 PM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > > > On Fri, May 16, 2014 at 04:09:59PM +0200, Stephane Eranian wrote:
> > > >> > +#define CACHE_LINESIZE       64
> > > >> I had something similar to your patch here in my original series for
> > > >> perf mem, but I never pushed it.
> > > >> I think this is a useful feature to have.
> > > >> However, I don't think you can hardcode the cache line size to 64.
> > > >> This is generic
> > > >> code. There may be architectures where the line size is different from 64.
> > > >> So I think you should add an option to change the default line size or provide
> > > >> an arch-specific definition.
> > > >
> > > > # cat /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
> > > > 64
> > > Excellent, then we should use that!
> > 
> > Would it make sense to create an accessory function that sets the size in
> > util/cpumap.c and provides it as an inline from util/cpumap.h?
> 
> sounds good,
> 
> btw so far I'll take patches 1-4 (after getting changelog update)
> and expecting v2 for 5,6 ;-)

Ok. Thanks!  What needs to be done for patch 5?  I have a patch 5.5?? that
does the cachline calculation that Stephane requested.  I just have to
find a way to dynamically handle the symbol lengths on output (and fix
that hang you see).

Cheers,
Don
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