RE: [RFC PATCH] pcie-designware: DT documentation update to clarify DT properties

[Karicheri, Muralidharan]

>-----Original Message-----
>From: Karicheri, Muralidharan
>Sent: Wednesday, May 21, 2014 6:52 PM
>To: jg1.han@xxxxxxxxxxx; xobs@xxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
>doc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; arnd@xxxxxxxx
>Cc: Karicheri, Muralidharan; Mohit Kumar; Pratyush Anand; Richard Zhu; ABRAHAM,
>KISHON VIJAY; Marek Vasut
>Subject: [RFC PATCH] pcie-designware: DT documentation update to clarify DT properties
>
>Current documentation is not clear enough about the mandatory bindings to be present in
>the device node of a snps,dw-pcie compatible pcie controller. In some cases the property is
>not present in all drivers.
>For example pcie_bus is specified as a clock, but only one of the driver uses it. This patch
>attempts to make the documentation consistent with current implementation so that it is
>clear enough for anyone who develops a dw-pcie compatible pcie driver.
>
>CC: Mohit Kumar <mohit.kumar@xxxxxx>
>CC: Jingoo Han <jg1.han@xxxxxxxxxxx>
>CC: Pratyush Anand <pratyush.anand@xxxxxx>
>CC: Richard Zhu <r65037@xxxxxxxxxxxxx>
>CC: Kishon Vijay Abraham I <kishon@xxxxxx>
>CC: Marek Vasut <marex@xxxxxxx>
>
>Signed-off-by: Murali Karicheri <m-karicheri2@xxxxxx>
>---
> .../devicetree/bindings/pci/designware-pcie.txt    |   10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
>diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>index d6fae13..8b9dc52 100644
>--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>@@ -4,12 +4,14 @@ Required properties:
> - compatible: should contain "snps,dw-pcie" to identify the
> 	core, plus an identifier for the specific instance, such
> 	as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
>-- reg: base addresses and lengths of the pcie controller,
>-	the phy controller, additional register for the phy controller.
>+- reg: base addresses and lengths of the pcie controller.
>+    index 0 - base address and length of RC's config space.
>+    index 1 and above: additional registers for the PCI controller
>+    that are specific to an implementation.
> - interrupts: interrupt values for level interrupt,
> 	pulse interrupt, special interrupt.
>-- clocks: from common clock binding: handle to pci clock.
>-- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
>+- clocks: from common clock binding: handle to list of pci clock.
>+- clock-names: from common clock binding: pci clock names: "pcie"
> - #address-cells: set to <3>
> - #size-cells: set to <2>
> - device_type: set to "pci"
>--
>1.7.9.5

+ Adding to the pci list.
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