Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold

[Andi Kleen]

> So, you're telling me this is a sanity check. That p->status can
> only have one bit set. Somehow that's not how I recall it working.

It can have multiple bits set. We don't know for sure for which
it is, but we should only deliver it for one anyways.

> The point is that a single PEBS record is enough for multiple
> events when the overflows occur simultaneously because they
> all get the same machine state which is correct.  A single entry
> also saves space in the buffer.

The CPU will generate multiple PEBS records in this case.
So if we delivered it for all you would overcount by factor 4x

[Again this is a very unlikely situation. Normally counters
are not in lock step]

-Andi

-- 
ak@xxxxxxxxxxxxxxx -- Speaking for myself only
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