Re: [PATCH v2 2/2] devicetree: Add Cadence WDT devicetree bindings documentation

[Mark Rutland]

On Tue, May 27, 2014 at 11:18:15AM +0100, Harini Katakam wrote:
> Add cadence-wdt bindings documentation.
> 
> Signed-off-by: Harini Katakam <harinik@xxxxxxxxxx>
> ---
> 
> v2:
> No changes
> 
> ---
>  .../devicetree/bindings/watchdog/cadence-wdt.txt   |   26 ++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/watchdog/cadence-wdt.txt
> 
> diff --git a/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt b/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt
> new file mode 100644
> index 0000000..1f7a732
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt
> @@ -0,0 +1,26 @@
> +Zynq Watchdog Device Tree Bindings
> +-------------------------------------------
> +
> +Required properties:
> +- compatible		: Should be "xlnx,zynq-wdt-r1p2" or "cdns,wdt-r1p2".

What's the difference? Can "cdns,wdt-r1p2" be a fallback for
"xlnx,zynq-wdt-r1p2"?

> +- clocks		: Clock phandles (see clock bindings for details).

Nit: Clocks aren't just phandles.

How many clocks? This implies several, the example shows one.

> +- reg			: Physical base address and size of WDT registers map.
> +- interrupts		: Property with a value describing the interrupt
> +			  number.

We know this is a property with a value. Describe what it logically is
(and optionally, the type is interrupt-sepcifier, though that gets
fuzzier with the interrupts-extended property).

> +- interrupt-parent	: Must be core interrupt controller.
> +
> +Optional properties
> +- reset			: Reset interrupt.

What does this mean? What type is this?

I have no idea if this is a boolean telling the OS to reset the
interrupt initially, or an index describing which interrupt is the reset
interrupt in either the interrupts property or some HW registers.

Cheers,
Mark.

> +- timeout-sec		: Watchdog timeout value (in seconds).
> +
> +Example:
> +
> +		wdt@f8005000 {
> +			compatible = "xlnx,zynq-wdt-r1p2";
> +			clocks = <&clkc 45>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 9 1>;
> +			reg = <0xf8005000 0x1000>;
> +			reset = <0>;
> +			timeout-sec = <10>;
> +		} ;
> -- 
> 1.7.9.5
> 
> 
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