Re: [PATCH 4/9] perf/x86: add cross-HT counter exclusion infrastructure

[Peter Zijlstra]

On Wed, Jun 04, 2014 at 11:34:13PM +0200, Stephane Eranian wrote:
> @@ -2020,12 +2050,29 @@ static void intel_pmu_cpu_starting(int cpu)
>  
>  	if (x86_pmu.lbr_sel_map)
>  		cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
> +
> +	if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
> +		for_each_cpu(i, topology_thread_cpumask(cpu)) {
> +			struct intel_excl_cntrs *c;
> +
> +			c = per_cpu(cpu_hw_events, i).excl_cntrs;
> +			if (c && c->core_id == core_id) {
> +				cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
> +				cpuc->excl_cntrs = c;
> +				cpuc->excl_thread_id = 1;
> +				break;
> +			}
> +		}
> +		cpuc->excl_cntrs->core_id = core_id;
> +		cpuc->excl_cntrs->refcnt++;
> +	}
>  }

This hard assumes theres only ever 2 threads, which is true and I
suppose more in arch/x86 will come apart the moment Intel makes a chip
with more, still, do we have topology_thread_id() or so to cure this?

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