Re: [RESEND PATCH v2] clk: exynos4: Add PPMU IP block source clocks.

[Tomasz Figa]

Hi Jonghwa,

On 11.06.2014 02:22, Jonghwa Lee wrote:
> Exynos4 has saveral PPMUs and each of them has operation clock which
> can be gated through CMU's SFR control.
> 
> New clocks are listed below. All clocks are added as a gate-typed clock.
> 
> CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L,
> CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1,
> CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU,
> CLK_PPMUACP,
> 
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@xxxxxxxxxxx>
> Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
> ---
>  V2 :
>     - Change clock definition order.
> 
>  drivers/clk/samsung/clk-exynos4.c   |   19 +++++++++++++++++++
>  include/dt-bindings/clock/exynos4.h |   18 ++++++++++++++++++
>  2 files changed, 37 insertions(+)

I have already queued the original v2 you sent, just waiting for
3.16-rc1 to be released to apply. :)

Best regards,
Tomasz
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