Re: [PATCH 7/7] x86: mm: set TLB flush tunable to sane value (33)

[Dave Hansen]

On 07/02/2014 11:16 AM, David Nellans wrote:
> Intuition here is that invalidate caused refills will almost always
> be serviced from the L2 or better since we've recently walked to
> modify the page needing flush and thus pre-warmed the caches for any
> refill? Or is this an artifact of the flush/refill test setup?

There are lots of caches in place, not just the CPU's normal L1/2/3
memory caches.  See "4.10.3 Paging-Structure Caches" in the Intel SDM.
I _believe_ TLB misses can be serviced from these caches and their
purpose is to avoid going out to memory (or the memory caches).

So I think the effect that we're seeing is from _all_ of the caches,
plus prefetching.  If you start a prefetch for a TLB miss before you
actually start to run the instruction needing the TLB entry, you will
pay less than the entire cost of going out to memory (or the memory caches).
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