[PATCH 2/4] pinctrl: qcom: Add documentation for pinctrl-qpnp binding

[Ivan T. Ivanov]

From: "Ivan T. Ivanov" <iivanov@xxxxxxxxxx>

DT binding documentation for qcom,pm8941-pinctrl and
qcom,pm8841-pinctrl drivers.

Signed-off-by: Ivan T. Ivanov <iivanov@xxxxxxxxxx>
---
 .../bindings/pinctrl/qcom,qpnp-pinctrl.txt         | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt
new file mode 100644
index 0000000..0b24860
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qpnp-pinctrl.txt
@@ -0,0 +1,78 @@
+Qualcomm Technologies (QTI) QPNP pinctrl controller
+
+Qualcomm Technologies (QTI) PMIC chips integrate SPMI based MPP (multiple
+purpose pin) and GPIO pin configuration hardware modules. These modules control
+the pin settings, including types/functions/directions/pulls/drive-strength/
+input/output, etc.
+
+They are two types of pins inside PMIC chips. Multi-Purpose Pin (MPP) and
+General Purpuse Pins (GPIO)
+
+MPP pins are supporting following functions:
+Digital Input, Digital Output, Analog Input, Analog Output and Current Sink
+
+GPIO pins are supporting following functions:
+Digital Input, Digital Output
+
+Required Properties:
+ - compatible: Should contain "qcom,pm8941-pinctrl" or "qcom,pm8841-pinctrl".
+ - reg:        MPP's configuration registers map offset
+               GPIO's configuration registers map offset - optional
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells : Should be two.
+                The first cell is the gpio pin number and the
+                second cell is used for optional parameters.
+
+Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Qualcomm's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+Valid functions for MPPs are gpio, mpp-ain, mpp-aout, mpp-cs.
+Valid function for GPIOs is gpio.
+
+Valid names for PM8841 pins are mpp1-mpp4.
+Valid names for PM8941 pins are mpp1-mpp8 and gpio1-gpio36.
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a GPIO pin configuration subnode:
+
+ pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
+ bias-high-impedance, drive-push-pull, drive-open-drain, drive-open-source,
+ input-enable, input-disable, power-source, output-low, output-high
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a MPP pin configuration subnode:
+
+ pins, function, bias-disable, bias-pull,up, drive-strength.
+ bias-high-impedance, input-enable, input-disable, power-source, output-low,
+ output-high,
+
+The following non-standard properties are valid to specify in a MPP pin
+configuration subnode:
+ qcom,ain-ctrl, qcom,aout-ctrl
+
+Example:
+
+	pm8941_pinctrl: pins@a000 {
+		compatible = "qcom,pm8941-pinctrl";
+		reg = <0xa000>, <0xc000>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
-- 
1.8.3.2

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