Re: [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124
From: Tuomas Tynkkynen
Date: Fri Jul 11 2014 - 11:29:17 EST
On 11/07/14 18:15, Thierry Reding wrote:
* PGP Signed by an unknown key
On Fri, Jul 11, 2014 at 06:11:41PM +0300, Tuomas Tynkkynen wrote:
On 11/07/14 17:57, Thierry Reding wrote:
I don't think that's going to work? The voltage scaling is handled in hw.
Do we have to handle it in hardware or can we opt to do it in software,
With the PLLX, voltage scaling is done entirely in SW. With the DFLL,
it's possible to stay in open-loop mode and do it in SW, but there's
not much point in that.
It's kind of ugly how we need to pass the address of the PMU and the
offset of the voltage control register to the DFLL which will then
initiate I2C transactions itself. I'm wondering if that plays well with
the I2C traffic originating from within the kernel.
On the hardware level, the two I2C controllers sharing the same pins
have knowledge of each other and won't start transmitting if the bus
is busy (something different from the usual I2C arbitration, that is).
I guess on the kernel side there could be a problem if the voltage
register is marked cached in the PMIC driver's regmap.
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