[PATCH v3 13/15] drivers: clk: st: STiH407: Support for clockgenA9

[Gabriel FERNANDEZ]

The patch added support for DT registration of ClockGenA9
It includes c32 type PLL.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@xxxxxxxxxx>
Signed-off-by: Olivier Bideau <olivier.bideau@xxxxxx>
Acked-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
---
 drivers/clk/st/clkgen-pll.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 5327a74..29769d7 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -216,6 +216,18 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
 	.ops		= &stm_pll3200c32_ops,
 };
 
+static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
+	/* 407 A9 */
+	.pdn_status	= CLKGEN_FIELD(0x1a8,	0x1,			0),
+	.locked_status	= CLKGEN_FIELD(0x87c,	0x1,			0),
+	.ndiv		= CLKGEN_FIELD(0x1b0,	C32_NDIV_MASK,		0),
+	.idf		= CLKGEN_FIELD(0x1a8,	C32_IDF_MASK,		25),
+	.num_odfs = 1,
+	.odf		= { CLKGEN_FIELD(0x1b0, C32_ODF_MASK,		8) },
+	.odf_gate	= { CLKGEN_FIELD(0x1ac, 0x1,			28) },
+	.ops		= &stm_pll3200c32_ops,
+};
+
 /**
  * DOC: Clock Generated by PLL, rate set and enabled by bootloader
  *
@@ -618,6 +630,10 @@ static struct of_device_id c32_pll_of_match[] = {
 		.compatible = "st,stih407-plls-c32-c0_1",
 		.data = &st_pll3200c32_407_c0_1,
 	},
+	{
+		.compatible = "st,stih407-plls-c32-a9",
+		.data = &st_pll3200c32_407_a9,
+	},
 	{}
 };
 
-- 
1.9.1

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