[tip:perf/urgent] perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge
From: tip-bot for Vince Weaver
Date: Wed Jul 16 2014 - 15:20:42 EST
Commit-ID: 1996388e9f4e3444db8273bc08d25164d2967c21
Gitweb: http://git.kernel.org/tip/1996388e9f4e3444db8273bc08d25164d2967c21
Author: Vince Weaver <vincent.weaver@xxxxxxxxx>
AuthorDate: Mon, 14 Jul 2014 15:33:25 -0400
Committer: Ingo Molnar <mingo@xxxxxxxxxx>
CommitDate: Wed, 16 Jul 2014 13:18:40 +0200
perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge
This was discussed back in February:
https://lkml.org/lkml/2014/2/18/956
But I never saw a patch come out of it.
On IvyBridge we share the SandyBridge cache event tables, but the
dTLB-load-miss event is not compatible. Patch it up after
the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK
Signed-off-by: Vince Weaver <vincent.weaver@xxxxxxxxx>
Signed-off-by: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Link: http://lkml.kernel.org/r/alpine.DEB.2.11.1407141528200.17214@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
---
arch/x86/kernel/cpu/perf_event_intel.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 07846d7..c206815 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2474,6 +2474,9 @@ __init int intel_pmu_init(void)
case 62: /* IvyBridge EP */
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
+ /* dTLB-load-misses on IVB is different than SNB */
+ hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
+
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
sizeof(hw_cache_extra_regs));
--
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