Re: [PATCH] x86, TSC: Add a software TSC offset

[Andy Lutomirski]

On Mon, Jul 21, 2014 at 3:30 PM, Borislav Petkov <bp@xxxxxxxxx> wrote:
> On Mon, Jul 21, 2014 at 03:13:33PM -0700, Andy Lutomirski wrote:
>> Ha.  Ha ha.  Muahaha.  Because IIRC this box is synced until the first
>> time it suspends.
>
> Sweet, TSCs get fumbled in some S-state or maybe SMI... Who TF knows.
>
> Well, I'm thinking upon resume, we run through smpboot which should do
> the tsc sync check again. Will have to test to see.

I have some reason to believe that this is almost an intentional bug
on the part of the BIOS vendor.

>
>> > diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
>> > index 94605c0e9cee..ad7d5e449c0b 100644
>> > --- a/arch/x86/include/asm/tsc.h
>> > +++ b/arch/x86/include/asm/tsc.h
>> > @@ -27,7 +27,9 @@ static inline cycles_t get_cycles(void)
>> >         if (!cpu_has_tsc)
>> >                 return 0;
>> >  #endif
>> > +       rdtsc_barrier();
>> >         rdtscll(ret);
>> > +       rdtsc_barrier();
>> >
>>
>> Only the first of these is necessary.  There was a long thread on this
>> a couple of years ago, and the conclusion was that the code in
>> vread_tsc in vclock_gettime.c is correct.
>
>          * The various CPU manuals are unclear
>          * as to whether rdtsc can be reordered with later loads,
>          * but no one has ever seen it happen.
>
> until some future uarch proves you wrong. :-)
>
> I guess we can try with one pre-fence only first although if we're doing
> one already, I can't imagine the post-one to be all that expensive since
> we've retired the whole inflight crap already anyway.
>

IIRC it was actually quite expensive, at least on Sandy Bridge.  Maybe
AMD is different.

Anyway, if some future uarch breaks this, I could resurrect my old
hack: do a TSC-dependent load prior to returning.  Loads are ordered,
and the hackish load can't be reordered wrt RDTSC due to
data-dependency, so we're in business :)

--Andy
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