Re: [PATCH] clk: ti: clk-7xx: Correct ABE DPLL configuration

From: Tero Kristo
Date: Tue Jul 29 2014 - 04:21:36 EST

On 07/29/2014 09:27 AM, Mike Turquette wrote:
Quoting Peter Ujfalusi (2014-07-14 03:10:28)
On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
Tero: can I have your ack for this patch or do you have further concerns?

Yea looks good to me, except for the fact that there is some work on getting
default rate/parent support through DT. I would like a comment from Mike about
the estimate when this can get in, and whether we should merge intermediate
solutions still like this.


On May 19 you said, "Thanks, queued for 3.16/ti-clk-drv." but I never
received that as part of the TI clock fixes. :-(

I've taken Sylwester's patch in for the DT-based assigned clock rates
and parents. You can find it in clk-next. (maybe you are still on
vacation? I don't know...)

Anyway, you can consider this patch acked by me, I'll let Mike to decide what
to do with it though.

Do you have anything against this patch? Since right now there is no other
ways to fix the ABE DPLL for dra7 it would be great if we could have this in
till we have the final solution. Also I'd like to point out that the original
frequency the ABE DPLL was not correct and renders the audio to be not usable
on the platform.

Mike: can we have this patch still pushed for 3.16? I can resend it right away
if you lost the original patch.


I have your original patch. No need to resend. Let's see if Tero
comments this week, otherwise I can take it with his previously supplied
Ack and send it off. Probably needs to be sent by Thursday at the

Oh yea, seems this got lost into the myriad of branches I have. I can push this on top of my for-v3.17/ti-clk-drv if you like.





Signed-off-by: Peter Ujfalusi <peter.ujfalusi@xxxxxx>
drivers/clk/ti/clk-7xx.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index f7e40734c819..19a55bf407dd 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -16,7 +16,7 @@
#include <linux/clkdev.h>
#include <linux/clk/ti.h>

-#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_ABE_DEFFREQ 180633600
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000

@@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);

+ dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
if (rc)

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