[PATCHv2 0/5] clk: samsung: exynos5410: Implementation of the PLL clocks

From: Humberto Silva Naves
Date: Thu Jul 31 2014 - 07:22:37 EST


This patch series slightly improves the exynos5410 clock driver. Below is
a list of changes introduced by the patch:
- Basic validation in the clock initialization routine
- Added resume/suspend handler
- Implemented some fixed rate clocks and changed the way "fin_pll" is defined
- Added the remaining PLL clocks

Changelog since v1:
* Split the reordering and addition of new constants into two different
commits, as suggested by Thomas Abraham. For details, see:
* The rate tables are only installed if the clock rate of the parent matches
a specific frequency of 24MHz. For details, please refer to:
* Added some fixed rate clocks.

Humberto Silva Naves (5):
clk: samsung: exynos5410: Add NULL pointer checks in clock init
clk: samsung: exynos5410: Organize register offset constants
clk: samsung: exynos5410: Add suspend/resume handling
clk: samsung: exynos5410: Add fixed rate clocks
clk: samsung: exynos5410: Added clocks DPLL, EPLL, IPLL, and VPLL

.../devicetree/bindings/clock/exynos5410-clock.txt | 17 +-
drivers/clk/samsung/clk-exynos5410.c | 437 ++++++++++++++++++--
include/dt-bindings/clock/exynos5410.h | 5 +
3 files changed, 430 insertions(+), 29 deletions(-)


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