Paul,Sorry for didn't check the header file, I'll change it to 65535 and resubmit.
On Thu, Aug 7, 2014 at 11:26 AM, Paul Zimmerman
<Paul.Zimmerman@xxxxxxxxxxxx> wrote:
Certainly it is documented in the header file to have a max of 65535:From: Kever Yang [mailto:kever.yang@xxxxxxxxx] On Behalf Of Kever YangHi Kever,
Sent: Thursday, August 07, 2014 2:35 AM
This patch add compatible data for dwc2 controller found on
rk3066, rk3188 and rk3288 processors from rockchip.
Signed-off-by: Kever Yang <kever.yang@xxxxxxxxxxxxxx>
Acked-by: Paul Zimmerman <paulz@xxxxxxxxxxxx>
---
Changes in v4:
- max_transfer_size change to 65536, this should be enough
for most transfer, the hardware auto-detect will set this
to 0x7ffff which may make dma_alloc_coherent fail when
non-dword aligned buf from driver like usbnet happen.
Did you test this change thoroughly? I have vague memories of any
value above 65535 causing problems, at least on my hardware. And I
see it is set to 65535 in both pci.c and platform.c. I could be
wrong, but I thought I should mention it.
* @max_transfer_size: The maximum transfer size supported, in bytes
* 2047 to 65,535
* Actual maximum value is autodetected and also
* the default.
You are right.
...but looking at the register definition that I see, the size can be
up to 19 bits. A 19-bit transfer far exceeds 65535. Do you remember
what the error was? Certainly I can imagine there being errors with
large calls to dma_alloc_coherent()...
I know that with Kever's change I can do USB Ethernet downloads, so it
is at least working to some degree. ...to me it feels like Kever
should resubmit with 65535 (to match the documentation) and then work
in the background to figure out what the max_transfer_size really
ought to be.
-Doug