Re: [PATCH 2/5] perf, x86: Document all Haswell models

[Peter Zijlstra]

On Wed, Aug 13, 2014 at 06:17:46PM -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> 
> Add names for each Haswell model as requested by Peter.
> 
> Signed-off-by: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> ---
>  arch/x86/kernel/cpu/perf_event_intel.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index ef6c8b7..03befdd 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2540,9 +2540,9 @@ __init int intel_pmu_init(void)
>  
>  
>  	case 60: /* Haswell Client */
> +	case 70: /* Crystall Well */
> +	case 63: /* Haswell Server */
> +	case 69: /* Haswell ULT */

So I googled Crystalwell, and I'm not sure I understand; is that
Haswell-H + GT3e or it that Haswell + GT3e, the distinction being that
there are also Desktop parts with Iris Pro 5200, such like the
Haswell-R.

Haswell Server, is that the single socket one, or is it like IVB both
the EP and EX parts?

And is 69 only the ULT or also the ULX parts?

Would something like this be accurate:?

	case 60: /* 22nm Haswell                        */
	case 70: /* 22nm Haswell + GT3e (Iris Pro 5200) */
	case 69: /* 22nm Haswell ULT                    */
	case 63: /* 22nm Haswell-EP/EX                  */

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