[PATCH 1/1] iommu/vt-d: Add new macros for invalidation event

[Li, Zhen-Hua]

According to intel's spec
        Intel Virtualization Technology for Directed I/O,
        Revision: 1.3 , February 2011,
        Chaper 10.4.25 to 10.4.28

There are four registers

        IECTL_REG   0xa0    Invalidation event control register
        IEDATA_REG  0xa4    Invalidation event data register
        IEADDR_REG  0xa8    Invalidation event address register
        IEUADDR_REG 0xac    Invalidation event upper address register

Through they are not used in kernel in the latest version, the defination
 should be added to kernel as well as other registers.

Signed-off-by: Li, Zhen-Hua <zhen-hual@xxxxxx>
---
 include/linux/intel-iommu.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index a65208a..15fafd5 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -56,6 +56,10 @@
 #define DMAR_IQ_SHIFT	4	/* Invalidation queue head/tail shift */
 #define DMAR_IQA_REG	0x90	/* Invalidation queue addr register */
 #define DMAR_ICS_REG	0x9c	/* Invalidation complete status register */
+#define DMAR_IECTL_REG	0xa0	/* Invalidation event control register */
+#define DMAR_IEDATA_REG	0xa4	/* Invalidation event data register */
+#define DMAR_IEADDR_REG	0xa8	/* Invalidation event address register */
+#define DMAR_IEUADDR_REG 0xac	/* Invalidation event upper address register */
 #define DMAR_IRTA_REG	0xb8    /* Interrupt remapping table addr register */
 
 #define OFFSET_STRIDE		(9)
-- 
2.0.0-rc0

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