Re: [PATCH v2 00/19] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages

[Joakim Tjernlund]

Christophe Leroy <christophe.leroy@xxxxxx> wrote on 2014/08/29 11:13:24:
> 
> This patchset:
> 1) provides several MMU TLB handling optimisation on MPC8xx.
> 2) adds support of 16k pages on MPC8xx.
> All changes have been successfully tested on a custom board equipped 
with MPC885
> 
> The two differences with first version of the patch are:
> 1) I removed the patch number 10, which was implementing a 16 bit 
alignment of the
> PGDIR. It is not worth potentially wasting up to 64k of memory just for 
removing one
> instruction (ori).
> 2) I managed to preserve r11 while calculating the level 2 address, 
therefore
> no more need to save r11 into CR.
> 
> Signed-off-by: Christophe Leroy <christophe.leroy@xxxxxx>
> Tested-by: Christophe Leroy <christophe.leroy@xxxxxx>

This looks good but I need to look harder, some minor critique 
though(already sent)
 
As you are optimizing I think the impl.of powerpc/8xx: Invalidate non 
present TLBs 
in 2.4 is better than 3.x, compare:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/powerpc/mm/fault.c?id=5efab4a02c89c252fb4cce097aafde5f8208dbfe
with
https://git.kernel.org/cgit/linux/kernel/git/wtarreau/linux-2.4.git/commit/?id=da5c5609e86fb12061f2c05a6ddd80ffc46592b2


This will free the TLB before you jump to xxx_page_fault which might need 
a TLB before invalidation
and it isolates this 8xx quirk in 8xx specific code.

 Jocke
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