Re: [PATCH] ASoC: fsl_spdif: don't change the root clock rate of spdif in driver

From: Shawn Guo
Date: Tue Sep 16 2014 - 22:31:47 EST

On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote:
> It's not supported in the clock API or just not implemented in our
> code? Can we just register a clock without CLK_SET_RATE_PARENT to
> achieve the purpose? (We are just trying to fix those PRED and PODF
> dividers when the driver calls set_rate to their GATE clock.)

It seems I misunderstood your question. Yes, if we drop flag
CLK_SET_RATE_PARENT for the gate clock in question, the rate change
request will not be propagated to upstream dividers.

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