[PATCH v3 16/17] documentation: memory-barriers: clarify relaxed io accessor semantics

From: Will Deacon
Date: Wed Sep 24 2014 - 13:20:52 EST

This patch extends the paragraph describing the relaxed read io accessors
so that the relaxed accessors are defined to be:

- Ordered with respect to each other if accessing the same peripheral

- Unordered with respect to normal memory accesses

- Unordered with respect to LOCK/UNLOCK operations

Whilst many architectures will provide stricter semantics, ARM, Alpha and
PPC can achieve significant performance gains by taking advantage of some
or all of the above relaxations.

Cc: Randy Dunlap <rdunlap@xxxxxxxxxxxxx>
Cc: Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx>
Cc: Paul E. McKenney <paulmck@xxxxxxxxxxxxxxxxxx>
Cc: David Howells <dhowells@xxxxxxxxxx>
Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
Documentation/memory-barriers.txt | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index a4de88fb55f0..6b2b4d735a5b 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -2461,10 +2461,15 @@ functions:
Please refer to the PCI specification for more information on interactions
between PCI transactions.

- (*) readX_relaxed()
- These are similar to readX(), but are not guaranteed to be ordered in any
- way. Be aware that there is no I/O read barrier available.
+ (*) readX_relaxed(), writeX_relaxed()
+ These are similar to readX() and writeX(), but provide weaker memory
+ ordering guarantees. Specifically, they do not guarantee ordering with
+ respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
+ ordering with respect to LOCK or UNLOCK operations. If the latter is
+ required, an mmiowb() barrier can be used. Note that relaxed accesses to
+ the same peripheral are guaranteed to be ordered with respect to each
+ other.

(*) ioreadX(), iowriteX()


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