Re: [PATCH 4/4] edac, amd64_edac: Add F15h M60h support

[Aravind Gopalakrishnan]

On 10/1/2014 10:45 AM, Borislav Petkov wrote:
> On Wed, Oct 01, 2014 at 10:32:58AM -0500, Aravind Gopalakrishnan wrote:
> > > > +			if (dcsm & 0x3) {
> > > > +				/* LRDIMMs */
> > > > +				edac_dbg(1, "  DIMM type: LRDIMM %dx rank multiply;"
> > > > +					 "CS = %d; all DIMMs support ECC: %s\n",
> > > > +					 (dcsm & 0x3), cs,
> > > > +					 (dclr & BIT(19)) ? "yes" : "no");
> > > Why do we need to iterate over the DRAM CS sets? Just for the rank
> > > multiplier, apparently. We dump those normally in read_dct_base_mask(),
> > > though.
> > It's not just for rank multiplier.. we find that it's LRDIMM only by
> > examining dcsm. Hence the iteration here..
> So we can look only at the first DCSM, no? Or are there systems with
> different types of LRDIMMs on one DCT?

Not AFAIK, But I'll ask to make sure.
If different LRDIMMs on one DCT don't exist, then sure, I'll modify the 
code to use first DCSM.

Regarding resend-
I'm not sure how you'll want the patches.. I just noticed a 
'edac-for-3.19' branch.
Would you prefer I based changes on top of this for merging purposes?
Or just resend the original 4 patches based off tip as usual?

Thanks,
-Aravind.
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