Re: [PATCH 2/2] spi: fsl-spi: Allow dynamic allocation of CPM1 parameter RAM

From: leroy christophe
Date: Wed Oct 08 2014 - 12:46:24 EST

Next message: Peter Zijlstra: "[PATCH] trace: Robustify wait loop"
Previous message: Steinar H. Gunderson: "Re: bisected: futex regression >= 3.14 - was - Slowdown due to threads bouncing between HT cores"
Next in thread: Scott Wood: "Re: [PATCH 2/2] spi: fsl-spi: Allow dynamic allocation of CPM1 parameter RAM"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Le 07/10/2014 02:19, Scott Wood a Ãcrit :

On Sat, 2014-10-04 at 12:15 +0200, christophe leroy wrote:

Le 03/10/2014 22:24, Scott Wood a Ãcrit :

On Fri, 2014-10-03 at 22:15 +0200, christophe leroy wrote:

Le 03/10/2014 16:44, Mark Brown a Ãcrit :

On Fri, Oct 03, 2014 at 02:56:09PM +0200, Christophe Leroy wrote:

+config CPM1_RELOCSPI
+ bool "Dynamic SPI relocation"
+ default n
+ help
+ On recent MPC8xx (at least MPC866 and MPC885) SPI can be relocated
+ without micropatch. This activates relocation to a dynamically
+ allocated area in the CPM Dual port RAM.
+ When combined with SPI relocation patch (for older MPC8xx) it avoids
+ the "loss" of additional Dual port RAM space just above the patch,
+ which might be needed for example when using the CPM QMC.

Something like this shouldn't be a compile time option. Either it
should be unconditional or it should be triggered in some system
specific manner (from DT, from knowing about other users or similar).

Can't be unconditional as older versions of mpc8xx (eg MPC860) don't
support relocation without a micropatch.
I have therefore submitted a v2 based on a DTS compatible property.

So the device tree change is about whether relocation is supported, not
whether it is required?

Indeed no, my intension is to say that relocation is requested. Do you
mean that it should then not use a compatible ?

The device tree describes hardware. It doesn't tell software how to use
that hardware.

Based on one of your other e-mails, I think what you want to say here is
that the old binding didn't describe the registers needed for
relocation, so the new compatible describes the new binding, rather than
requesting that software do a relocation. Software that sees the new
binding could choose to relocate, or just choose to read the current
offset from the register.

Not exactly.
The old binding does describe the entire default param RAM (0x3d80 size 0x30). The relocation index is within this param RAM at 0x3dac.
So the old binding is enough to allow relocation.
The issue today with the driver (hence my first patch) is that the driver reads the relocation index but takes a wrong decision if the index is 0: it assumes that an nul index means that a param RAM shall be allocated, which is wrong. A nul index means that the component doesn't support relocation, so the default param RAM shall be used. The function used for that is supposed to return the index. So when the index is null, I need to calculate it.

Now, it can't be the SPI driver by itself that decide if he has to relocate or not. Because it depends whether I need to relocate or not. There is no point in waisting another area of the dualport RAM if I don't need to use SCC2 in a mode that overlaps the SPI parameter RAM.

Today on the old MPC8xx, a microcode patch is needed in order to be able to relocate, and relocated address is directly fixed by the code handling the patch (sysdev/micropatch.c). The patch loading function is call very early in the boot process by cpm_reset() which is call by the xxx_setup_arch().
I have two issues with the way it is done today:
1/ the address which in hard coded is the micropatch loading function() is within the area for descripters for the QMC, so I would need to use another address.
2/ for new MPC8xx which don't need microcode patch, I have no way today to relocate.

I have the same issue with the relocation of SMC1. Today when we activate SMC1 relocation microcode patch, the loading function has a hard coded relocation area for SMC1 which is the area dedicated to the MPC8xx DSP. It means that I need to change it as I want to use the DSP.

Would it be acceptable to define a fixed relocation address in the Kconfig in which we select microcode patch (arch/powerpc/platforms/8xx), instead of having it hardcoded in micropatch.c ?

Or maybe it would be possible to select which microcode patch we want/need via the device tree and which address shall be used for relocation ? What would you suggest to describe it ?

How about checking for the existing specific-SoC compatibles?

What do you mean ?

Look for "fsl,mpc885-cpm-i2c" etc. Or, if you didn't follow that
pattern (remember, I can't see your device tree!), look for
"fsl,mpc885-cpm" or "fsl,mpc866-cpm" in the parent node. It's moot
though, if the device tree also needs to be modified to describe the
register used to relocate.

-Scott

I'm not sure I understood your question.
My full device tree below

Christophe

/*
* MIA ethernet Device Tree Source
*
* Copyright 2011 CSSI, Inc
*/

/dts-v1/;

/ {
model = "MIAE";
compatible = "fsl,cmpc885", "fsl,mod885";
#address-cells = <1>;
#size-cells = <1>;

aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
mdio = &phy;
serial0 = &smc1;
};

cpus {
#address-cells = <1>;
#size-cells = <0>;

PowerPC,885@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <16>; // 16 bytes
i-cache-line-size = <16>; // 16 bytes
d-cache-size = <8192>;
i-cache-size = <8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <15 2>; // decrementer interrupt
interrupt-parent = <&PIC>;
};
};

memory {
device_type = "memory";
reg = <0x0 0x0>; // defined by U-BOOT
};

localbus@ff000100 {
compatible = "fsl,cmpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xff000100 0x40>; // ORx and BRx register

ranges = <0 0x0 0x40000000 0x00400000 // Boot Flash
1 0x0 0x00000000 0x08000000 // SDRAM
2 0x0 0xc0000000 0x00008000 // Nand Flash
3 0x0 0xe0000000 0x00010000 // DPRAM
4 0x0 0xd0000000 0x10000000 // Periphs
5 0x0 0xc8000000 0x00008000 // CPLD
6 0x0 0x80000000 0x00008000 // mezzanine
7 0x0 0xf0000000 0x00008000>; // DSP

flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x00000000 0x400000>;
bank-width = <2>;
device-width = <2>;
partition@0 {
label = "boot";
reg = <0x0 0x50000>;
};
partition@50000 {
label = "env";
reg = <0x50000 0x10000>;
};
partition@60000 {
label = "blob";
reg = <0x60000 0x30000>;
};
partition@90000 {
label = "kernel";
reg = <0x90000 0x370000>;
};
};

nand@2,0 {
compatible = "s3k,cmpc885-nand";
reg = <2 0x0 0x01>;
#address-cells = <1>;
#size-cells = <1>;
gpios = <&CPM1_PIO_D 12 1 // CLE
&CPM1_PIO_D 13 1 // ALE
&CPM1_PIO_D 15 1>; // NCE
};

cpld-cmpc@5,0000000 { // Driver KNL
#address-cells = <1>;
#size-cells = <1>;
compatible = "s3k,mcr3000-cpld-cmpc";
reg = <5 0x0 0x10>;
};

cpld-mpc@5,0000000 { // Driver LDB (deviendra obsolete)
#address-cells = <1>;
#size-cells = <1>;
compatible = "s3k,mcr3000-cpld-mpc";
reg = <5 0x0 0x10>;
};

fpga-m@4,0000000 { // Driver LDB (deviendra peut etre obsolete)
#address-cells = <1>;
#size-cells = <1>;
compatible = "s3k,mcr3000-fpga-m";
reg = <4 0x0000000 0x60>;
ranges = <0 4 0x0000000 0x60>;
ident: gpio-controller@00 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x00 2>;
gpio-controller;
};
ver: gpio-controller@02 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x02 2>;
gpio-controller;
};
tst: gpio-controller@04 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x04 2>;
gpio-controller;
};
rst: gpio-controller@10 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x10 2>;
gpio-controller;
};
mask1: gpio-controller@20 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x20 2>;
gpio-controller;
};
mask2: gpio-controller@22 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x22 2>;
gpio-controller;
};
pend1: gpio-controller@24 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x24 2>;
gpio-controller;
};
pend2: gpio-controller@26 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x26 2>;
gpio-controller;
};
acq1: gpio-controller@28 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x28 2>;
gpio-controller;
};
acq2: gpio-controller@2A {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x2A 2>;
gpio-controller;
};
ctrl: gpio-controller@2C {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x2C 2>;
gpio-controller;
};
torin: gpio-controller@30 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x30 2>;
interrupts = <255 255 255 255 255 5 6 7 8 9 10 11 12 13 14 15>;
interrupt-parent = <&FPGAM_PIC>;
gpio-controller;
};
torout: gpio-controller@32 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x32 2>;
gpio-controller;
};
liens: gpio-controller@34 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-direct-gpio";
reg = <0x34 2>;
gpio-controller;
};
gen: gpio-controller@40 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x40 2>;
gpio-controller;
};
far: gpio-controller@42 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x42 2>;
interrupts = <255 255 255 255 255 255 255 255 255 255 255 0 28 30 29 31>;
interrupt-parent = <&FPGAM_PIC>;
gpio-controller;
};
fav: gpio-controller@44 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x44 2>;
interrupts = <255 255 255 255 255 255 255 255 17 25 19 27 16 24 18 26>;
interrupt-parent = <&FPGAM_PIC>;
gpio-controller;
};
statpll: gpio-controller@50 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x50 2>;
gpio-controller;
};
srcpll: gpio-controller@52 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x52 2>;
gpio-controller;
};
etatref: gpio-controller@54 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-fpga-m-gpio";
reg = <0x54 2>;
gpio-controller;
};
FPGAM_PIC: pic@22 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupts = <6 1>;
interrupt-parent = <&PIC>;
reg = <0x00 0x60>; /* Mappage registres FPGAM */
compatible = "s3k,miae-pic";
};
};

PRES_EQUT {
compatible = "ident-gpio-pres-equt";
interrupts = <17 19 16 18>; /* Equipt 1 et 2 */
interrupt-parent = <&FPGAM_PIC>;
reg = <4 0x44 2>;
gpios = <&fav 8 1 /* Presence ÂCasque1 */
&fav 10 1 /* Presence ÂMain1 */
&fav 12 1 /* Presence ÂCasque2 */
&fav 14 1>; /* Presence ÂMain2 */
};

led_pwr {
compatible = "s3k,miae-led-pwr";
gpios = <&fav 6 2 /* led multi verte */
&fav 7 0>; /* led multi rouge */
};

e1@4,2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s3k,mcr3000-e1";
reg = <4 0x2000000 0xFF>;
interrupts = <8 1>;
interrupt-parent = <&PIC>;
};

e1-wan@4,2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,pef2256";
reg = <4 0x2000000 0xFF>;
interrupts = <8 1>;
interrupt-parent = <&PIC>;
};

GPIO {
/* 0 = sortie initialisee active */
/* 1 = entree */
/* 2 = sortie initialisee inactive */
compatible = "s3k,gpios-appli";
reg = <4 0x42 4>;
gpios = <&torin 15 1 // TOR in 1
&torin 14 1 // TOR in 2
&torin 13 1 // TOR in 3
&torin 12 1 // TOR in 4
&torin 11 1 // TOR in 5
&torin 10 1 // TOR in 6
&torin 9 1 // TOR in 7
&torin 8 1 // TOR in 8
&torin 7 1 // TOR in 9
&torin 6 1 // TOR in 10
&torin 5 1 // TOR in 11
&torout 15 2 // TOR out 1
&torout 14 2 // TOR out 2
&torout 13 2 // TOR out 3
&torout 12 2 // TOR out 4
&torout 11 2 // TOR out 5
&torout 10 2 // TOR out 6
&torout 9 2 // TOR out 7
&torout 8 2 // TOR out 8
&far 15 1 // BP Alt
&far 13 1 // Alternat 1
&far 14 1 // Alternat 2
&far 12 1 // Alternat Combine
&far 11 1 // Presence Combine
&fav 11 1 // Alternat ÂMain1
&fav 15 1 // Alternat ÂMain2
&fav 9 1 // Alternat ÂCasque1
&fav 13 1>; // Alternat ÂCasque2
};

GPIO_CA_CLA {
compatible = "s3k,gpios-def-ca", "cs,mia-far";
far-id = <0 7>;
names = "tor_in_1",
"tor_in_2",
"tor_in_3",
"tor_in_4",
"tor_in_5",
"tor_in_6",
"tor_in_7",
"tor_in_8",
"tor_in_9",
"tor_in_10",
"tor_in_11",
"tor_out_1",
"tor_out_2",
"tor_out_3",
"tor_out_4",
"tor_out_5",
"tor_out_6",
"tor_out_7",
"tor_out_8",
"alt_bp",
"tor_in_13", // Alternat 1
"tor_in_14", // Alternat 2
"alt_ucomb",
"pres_ucomb";
codec = "Rec. In 1",
"Interco In 1",
"Rec. In 2",
"Interco In 2",
"Micro ITH",
"Audio OPT 1",
"Audio OPT 2",
"Micro Combine",
"Rec. Out 1",
"Interco Out 1",
"Rec. Out 2",
"Interco Out 2",
"HP ITH",
"HP 1",
"HP 2",
"Ecoute Combine";
};

GPIO_FAV_CLA {
compatible = "s3k,gpios-def-fav", "cs,mia-fav";
fav-id = <7>;
names = "alt_umain_a",
"alt_umain_b",
"alt_ucasque_a",
"alt_ucasque_b";
pres = "pres_ucasque_a",
"pres_umain_a",
"pres_ucasque_b",
"pres_umain_b";
codec = "Micro Casque_a",
"Micro Main_a",
"Micro Casque_b",
"Micro Main_b",
"Ec. droite Casque_a",
"Ec. gauche Casque_a",
"Ec. droite Casque_b",
"Ec. gauche Casque_b";
};

GPIO_CA_NVCS {
compatible = "s3k,gpios-def-ca", "cs,mia-far";
far-id = <1>;
names = "tor_in_audio_1",
"tor_in_audio_2",
"tor_in_audio_3",
"tor_in_audio_4",
"tor_in_5",
"alt_pedale_1",
"alt_pedale_2",
"dec_ucomb",
"tor_in_9",
"tor_in_10",
"alt_aith",
"tor_out_audio_1",
"tor_out_audio_2",
"tor_out_audio_3",
"tor_out_audio_4",
"tor_out_5",
"tor_out_6",
"none",
"none",
"alt_bp",
"tor_in_13", // Alternat 1
"tor_in_14", // Alternat 2
"alt_ucomb",
"pres_ucomb";
codec = "Audio In 1",
"Audio In 2",
"Audio In 3",
"Audio In 4",
"Micro ITH",
"Audio OPT 1",
"Audio OPT 2",
"Micro Combine",
"Audio Out 1",
"Audio Out 2",
"Audio Out 3",
"Audio Out 4",
"Audio Out 5",
"HP 1",
"HP 2",
"Ecoute Combine";
};

GPIO_FAV_NVCS {
compatible = "s3k,gpios-def-fav", "cs,mia-fav";
fav-id = <3 5 6>;
names = "alt_umain_a",
"alt_umain_b",
"alt_ucasque_a",
"alt_ucasque_b";
pres = "pres_ucasque_a",
"pres_umain_a",
"pres_ucasque_b",
"pres_umain_b";
codec = "Micro Casque_a",
"Micro Main_a",
"Micro Casque_b",
"Micro Main_b",
"Ec. droite Casque_a",
"Ec. gauche Casque_a",
"Ec. droite Casque_b",
"Ec. gauche Casque_b";
};

GPIO_CA_GW {
compatible = "s3k,gpios-def-ca", "cs,mia-far";
far-id = <4>;
names = "tor_in_1",
"tor_in_2",
"tor_in_3",
"tor_in_4",
"tor_in_5",
"tor_in_6",
"tor_in_7",
"none",
"none",
"dptt",
"pt_ct",
"tor_out_1",
"tor_out_2",
"tor_out_3",
"tor_out_4",
"tor_out_5",
"tor_out_6",
"tor_out_7",
"cgc",
"none",
"none",
"none",
"none",
"none";
codec = "Audio In 1",
"Audio In 2",
"Audio In 3",
"Audio In 4",
"Audio In 5",
"Audio In 6",
"Audio In 7",
"Audio In 8",
"Audio Out 1",
"Audio Out 2",
"Audio Out 3",
"Audio Out 4",
"not used",
"not used",
"not used",
"not used";
};

GPIO_FAV_GW {
compatible = "s3k,gpios-def-fav", "cs,mia-fav";
fav-id = <4>;
names = "none",
"none",
"none",
"none";
pres = "none",
"none",
"none",
"none";
codec = "Micro Casque_a",
"not used",
"not used",
"not used",
"Ec. droite Casque_a",
"not used",
"not used",
"not used";
};

IDENT_EQUIPT_NVCS {
compatible = "ident-equipt-fav", "cs,mia-fav";
fav-id = <3 5 6>;
infos = "22", /* nombre d'Ãquipements possibles */
/* bornes min et max, niveaux in et out en dB, croissement TS, type casque */
"0", "340", "-27", "-10", "no", "yes", /* equipement 1 */
"341", "420", "-27", "-10", "no", "yes", /* equipement 2 */
"421", "502", "-27", "-10", "no", "yes", /* equipement 3 */
"503", "578", "-27", "-10", "no", "yes", /* equipement 4 */
"579", "682", "-27", "-10", "no", "yes", /* equipement 5 */
"683", "804", "-27", "-10", "no", "yes", /* equipement 6 */
"805", "908", "-7", "-17", "yes", "yes", /* equipement 7 */
"909", "1016", "-27", "-10", "no", "yes", /* equipement 8 */
"1017", "1120", "-27", "-10", "no", "yes", /* equipement 9 */
"1121", "1232", "-27", "-10", "no", "yes", /* equipement 10 */
"1233", "1392", "-27", "-10", "no", "yes", /* equipement 11 */
"1393", "1523", "-23", "-1", "no", "yes", /* equipement 12 */
"1524", "1664", "-27", "-10", "no", "yes", /* equipement 13 */
"1665", "1786", "-27", "-10", "no", "yes", /* equipement 14 */
"1787", "1954", "-27", "-10", "no", "yes", /* equipement 15 */
"1955", "2194", "-27", "-10", "no", "yes", /* equipement 16 */
"2195", "2396", "-27", "-10", "no", "yes", /* equipement 17 */
"2397", "2556", "-27", "-10", "no", "yes", /* equipement 18 */
"2557", "2738", "-27", "-10", "no", "yes", /* equipement 19 */
"2739", "2966", "-27", "-10", "no", "yes", /* equipement 20 */
"2967", "3156", "-11", "-10", "no", "no", /* equipement 21 */
"3157", "4095", "-27", "-10", "no", "yes"; /* sans equipement */
};

FAV_CS_SPI: gpio-controller@dummy0 {
#gpio-cells = <2>;
compatible = "cs-fav-poste";
gpio-controller;
reg = <4 0x44 2>; /* necessaire mais non utilise */
gpios = <&fav 5 1 /* CS FAV */
&fav 4 1 /* CS Ident equipement */
&fav 3 1>; /* CS FPGA */
};

POT_A_NVCS {
compatible = "pot-miae", "cs,mia-fav";
fav-id = <5 6>;
user-name = "pot_a";
dev-name = "ad7923";
io-channels = <&iio 0>;
io-channel-names = "channel_0";
dev-channel = "channel_0";
};
POT_B_NVCS {
compatible = "pot-miae", "cs,mia-fav";
fav-id = <5 6>;
user-name = "pot_b";
dev-name = "ad7923";
io-channels = <&iio 1>;
io-channel-names = "channel_1";
dev-channel = "channel_1";
};

POT_A_PO {
compatible = "pot-miae", "cs,mia-fav";
fav-id = <3>;
user-name = "pot_a";
dev-name = "none";
dev-channel = "channel_0";
};
POT_B_PO {
compatible = "pot-miae", "cs,mia-fav";
fav-id = <3>;
user-name = "pot_b";
dev-name = "none";
dev-channel = "channel_1";
};
POT_C_PO {
compatible = "pot-miae", "cs,mia-fav";
fav-id = <3>;
user-name = "pot_c";
dev-name = "none";
dev-channel = "channel_2";
};
POT_D_PO {
compatible = "pot-miae", "cs,mia-fav";
fav-id = <3>;
user-name = "pot_d";
dev-name = "none";
dev-channel = "channel_3";
};
};

soc@ff000000 {
compatible = "fsl,mpc885", "fsl,pq1-soc";
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x0 0xff000000 0x28000>;
bus-frequency = <0>;
clock-frequency = <0>;

WDT: watchdon@0 {
compatible = "fsl,mpc823-wdt";
reg = <0x0 0x10>;
};

phy: mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
reg = <0xe00 0x188>;
#address-cells = <1>;
#size-cells = <0>;

PHY1: ethernet-phy@1 {
interrupts = <2 1>;
interrupt-parent = <&PIC>;
reg = <0x1>;
device_type = "ethernet-phy";
};

PHY2: ethernet-phy@2 {
interrupts = <2 1>;
interrupt-parent = <&PIC>;
reg = <0x3>;
device_type = "ethernet-phy";
};

PHY3: ethernet-phy@3 {
interrupts = <2 1>;
interrupt-parent = <&PIC>;
reg = <0x2>;
device_type = "ethernet-phy";
};
};

eth0: ethernet@e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet", "fsl,pq1-fec-enet";
reg = <0xe00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <5 1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <0>;
};

eth1: ethernet@1e00 {
device_type = "network";
compatible = "fsl,mpc885-fec-enet", "fsl,pq1-fec-enet";
reg = <0x1e00 0x188>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY2 &PHY3>;
linux,network-index = <1>;
gpios = <&CPM1_PIO_E 18 1>;
PHY-disable = "isolate";
};

PIC: pic@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x24>;
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};

SIT: sit@200 {
compatible = "fsl,mpc866-sit", "fsl,pq1-sit";
reg = <0x200 0x80>;
interrupts = <11 1>;
interrupt-parent = <&PIC>;
};

cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
ranges;
reg = <0x9c0 0x40>;
brg-frequency = <0>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;

muram@2000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2000 0x2000>;

data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0x0 0x1c00>;
};
};

brg@9f0 {
compatible = "fsl,mpc885-brg", "fsl,cpm1-brg", "fsl,cpm-brg";
reg = <0x9f0 0x10>;
clock-frequency = <0>;
};

CPM_PIC: pic@930 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupts = <3 2 0 2>;
interrupt-parent = <&PIC>;
reg = <0x930 0x20>;
compatible = "fsl,mpc885-cpm-pic", "fsl,cpm1-pic";
};

CPM1_PIO_A: gpio-controller@950 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-a";
reg = <0x950 0x10>;
gpio-controller;
};

CPM1_PIO_B: gpio-controller@ab8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-b";
reg = <0xab8 0x10>;
gpio-controller;
};

CPM1_PIO_C: gpio-controller@960 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-c";
reg = <0x960 0x10>;
interrupts = <0 0 0 0 1 2 6 9 10 11 14 15 23 24 26 31>;
interrupt-parent = <&CPM_PIC>;
gpio-controller;
};

CPM1_PIO_D: gpio-controller@970 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-d";
reg = <0x970 0x10>;
gpio-controller;
};

CPM1_PIO_E: gpio-controller@ac8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-e";
reg = <0xac8 0x18>;
gpio-controller;
};

dsp1: dsp1@900 {
device_type = "dsp";
compatible = "fsl,cpm1-dsp";
reg = <0x900 0x30 0x3ec0 0x40>;
interrupts = <22>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-dsp = <1>;
fsl,cpm-command = <0x90>;
};

dsp2: dsp2@900 {
device_type = "dsp";
compatible = "fsl,cpm1-dsp";
reg = <0x900 0x30 0x3fc0 0x40>;
interrupts = <22>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-dsp = <2>;
fsl,cpm-command = <0xd0>;
};

tsa: tsa@9c0 {
compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
reg = <0x9c0 0x440 0x930 0x20>;
/* parametres possible : none, SCC3, SCC4 (ou SMC2 si defini) */
scc_tdm = "SCC4";
/* vitesse bus numerique 4 ou 8 MHz */
data_rate = <4>;
};

smc1: serial@a80 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart", "fsl,cpm1-smc-uart";
reg = <0xa80 0x10 0x3e80 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <4>;
fsl,cpm-command = <0x90>;
};

scc2: serial@a20 {
device_type = "serial";
compatible = "fsl,mpc885-scc-uart", "fsl,cpm1-scc-uart";
reg = <0xa20 0x20 0x3d00 0x80>;
interrupts = <29>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0x40>;
gpios = <&CPM1_PIO_C 9 1 /* CTS2 */
&CPM1_PIO_B 18 1>; /* RTS2 */
};

smc2: serial@a90 {
device_type = "serial";
compatible = "fsl,mpc885-smc-uart", "fsl,cpm1-smc-uart", "cs,mia-far";
reg = <0xa90 0x10 0x3f80 0x40>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <3>;
fsl,cpm-command = <0xd0>;
gpios = <&liens 3 1 /* CTS */
&liens 4 1>; /* RTS */
far-id = <4>;
};

scc3: serial@a40 {
device_type = "serial";
compatible = "fsl,mpc885-scc-uart", "fsl,cpm1-scc-uart", "cs,mia-far";
reg = <0xa40 0x20 0x3e00 0x80>;
interrupts = <28>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0x80>;
gpios = <&CPM1_PIO_C 5 1 /* CTS3 */
&CPM1_PIO_D 7 1>; /* RTS3 */
far-id = <4>;
};

scc3wb: wb@a40 {
device_type = "wb_scc";
wb_name = "scc3";
compatible = "cs,wb-scc", "cs,mia-far";
reg = <0xa40 0x20 0x3e00 0x80>;
interrupts = <28 2>; /* scc, cts */
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0x80>;
gpios = <&CPM1_PIO_C 5 1 /* CTS3 */
&CPM1_PIO_D 7 1>; /* RTS3 */
far-id = <4>;
};

scc4t: tdm@a60 {
device_type = "tdm";
tdm_name = "scc4";
compatible = "fsl,mpc885-scc-tdm", "fsl,cpm1-scc-tdm";
reg = <0xa60 0x20 0x3f00 0x80>;
interrupts = <27>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-command = <0xc0>;
};

smc2_9b: smc@a90 {
device_type = "smc_9bits";
compatible = "cs,smc-9bits", "cs,mia-far";
reg = <0xa90 0x10 0x3f80 0x40 0x9c0 0x440>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <3>;
fsl,cpm-command = <0xd0>;
gpios = <&liens 12 1 /* CTS */
&liens 11 1>; /* RTS */
far-id = <4>;
};

spi: spi@a80 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,spi", "fsl,cpm1-spi";
reg = <0xa80 0x30 0x3d80 0x30>;
interrupts = <5>;
interrupt-parent = <&CPM_PIC>;
mode = "cpu";
gpios = <&CPM1_PIO_C 4 1 /* SICOFI 1 */
&CPM1_PIO_B 23 1 /* TEMP MCR */
&CPM1_PIO_C 8 1 /* SICOFI 2 */
&CPM1_PIO_C 12 1 /* EEPROM MIAE */
&CPM1_PIO_D 6 1 /* SICOFI 3 */
&CPM1_PIO_B 14 1 /* TEMP MPC885 */
&CPM1_PIO_B 21 1 /* EEPROM CMPC885 */
&FAV_CS_SPI 1 1 /* FAV SPI */
&FAV_CS_SPI 2 1>; /* FAV POSTE FPGA */
sicofi@0 {
compatible = "infineon,miae-sicofi", "cs,mia-far";
far-id = <0 2 3 4 5 6 7>;
spi-max-frequency = <1000000>;
reg = <0>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_1";
analog_in = "-2dB -2dB -2dB -2dB";
analog_out = "6dB 6dB 6dB 6dB";
niveau_in = "-10dB -10dB -10dB -10dB";
niveau_out = "-10dB -10dB -10dB -10dB";
};
sicofi_nvcs@0 {
compatible = "infineon,miae-sicofi", "cs,mia-far";
far-id = <1>;
spi-max-frequency = <1000000>;
reg = <0>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_1";
analog_in = "-2dB -2dB -2dB -2dB";
analog_out = "0dB 0dB 0dB 0dB";
niveau_in = "-10dB -10dB -10dB -10dB";
niveau_out = "-10dB -10dB -10dB -10dB";
};
lm74@1 {
compatible = "ns,lm74";
spi-max-frequency = <1000000>;
reg = <1>;
spi-cs-high;
};
sicofi@2 {
compatible = "infineon,miae-sicofi", "cs,mia-far";
far-id = <0 2 3 5 6 7>;
spi-max-frequency = <1000000>;
reg = <2>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_2";
analog_in = "-2dB 0dB 0dB 12dB";
analog_out = "3dB 3dB 3dB 4,5dB";
niveau_in = "-10dB -10dB -10dB -31dB";
niveau_out = "-10dB -10dB -10dB -10dB";
};
sicofi_nvcs@2 {
compatible = "infineon,miae-sicofi", "cs,mia-far";
far-id = <1>;
spi-max-frequency = <1000000>;
reg = <2>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_2";
analog_in = "-2dB 0dB 0dB 18dB";
analog_out = "6dB 3dB 3dB 4,5dB";
niveau_in = "-10dB -10dB -10dB -37dB";
niveau_out = "-10dB -10dB -10dB -10dB";
};
sicofi_gw@2 {
compatible = "infineon,miae-sicofi", "cs,mia-far";
far-id = <4>;
spi-max-frequency = <1000000>;
reg = <2>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_2";
analog_in = "-3dB -3dB -3dB -3dB";
analog_out = "3dB 3dB 3dB 3dB";
niveau_in = "-10dB -10dB -10dB -10dB";
niveau_out = "-10dB -10dB -10dB -10dB";
};
eeprom@3 {
compatible = "atmel,at25", "cs,eeprom";
spi-max-frequency = <1000000>;
reg = <3>;
spi-cs-high;
at25,byte-len = <1024>;
at25,addr-mode = <2>;
at25,page-size = <32>;
};
sicofi@4 {
compatible = "infineon,miae-sicofi", "cs,mia-fav";
fav-id = <0 1 2 4 7>;
spi-max-frequency = <1000000>;
reg = <4>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_3";
analog_in = "12dB -7dB 12dB -7dB";
analog_out = "6dB 6dB 6dB 6dB";
niveau_in = "-27dB -8dB -27dB -8dB";
niveau_out = "-10dB -10dB -10dB -10dB";
};
sicofi_nvcs@4 {
compatible = "infineon,miae-sicofi", "cs,mia-fav";
fav-id = <5 6>;
spi-max-frequency = <1000000>;
reg = <4>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_3";
analog_in = "12dB -7dB 12dB -7dB";
analog_out = "6dB 6dB 6dB 6dB";
niveau_in = "-27dB -8dB -27dB -8dB";
niveau_out = "-10dB -10dB -10dB -10dB";
io-channels = <&iio 2>, <&iio 3>;
iio-name = "ad7923";
io-channel-names = "channel_2", "channel_3";
iio-channel = "channel_2", "channel_3";
};
sicofi_postes@4 {
compatible = "infineon,miae-sicofi", "cs,mia-fav";
fav-id = <3>;
spi-max-frequency = <1000000>;
reg = <4>;
spi-cs-high;
spi-cpha;
spi-troll;
name_codec = "codec_3";
analog_in = "12dB -7dB 12dB -7dB";
analog_out = "6dB 6dB 6dB 6dB";
niveau_in = "-27dB -8dB -27dB -8dB";
niveau_out = "-10dB -10dB -10dB -10dB";
io-channels = <&iio 0>, <&iio 1>;
iio-name = "ad7923";
io-channel-names = "channel_0", "channel_1";
iio-channel = "channel_0", "channel_1";
};
lm74@5 {
compatible = "ns,lm74";
spi-max-frequency = <1000000>;
reg = <5>;
spi-cs-high;
};
eeprom@6 {
compatible = "atmel,at25", "cs,eeprom";
spi-max-frequency = <1000000>;
reg = <6>;
spi-cs-high;
at25,byte-len = <1024>;
at25,addr-mode = <2>;
at25,page-size = <32>;
};
iio: csfav@7 {
compatible = "iio,ad7923", "cs,mia-fav";
spi-max-frequency = <2000000>;
reg = <7>;
spi-cs-high;
spi-cpol;
fav-id = <3 5 6>;
#io-channel-cells = <1>;
};
gpiofav: csfavgw@7 {
compatible = "gpio,max7301", "cs,mia-fav";
spi-max-frequency = <2000000>;
reg = <7>;
spi-cs-high;
#gpio-cells = <2>;
gpio-controller;
fav-id = <4>;
};
csfavfpga@8 {
compatible = "cs,fpga-poste", "cs,mia-fav";
spi-max-frequency = <2000000>;
reg = <8>;
spi-cs-high;
fav-id = <3>;
};
};

dummy_pio {
compatible = "s3k,dummy_pio";
reg = <0xa980 0x40>;
};

dummy: gpio-controller@dummygpio {
#gpio-cells = <2>;
compatible = "s3k,dummy-gpio";
reg = <0x2 0x1>; /* necessaire mais non utilise */
gpio-controller;
};

gpio-leds {
compatible = "gpio-leds", "cs,mia-fav";
fav-id = <4>;
port_31 {
label = "favgw:red:1";
gpios = <&gpiofav 27 1>;
};
port_30 {
label = "favgw:red:2";
gpios = <&gpiofav 26 1>;
};
port_29 {
label = "favgw:red:3";
gpios = <&gpiofav 25 1>;
};
port_28 {
label = "favgw:red:4";
gpios = <&gpiofav 24 1>;
};
port_27 {
label = "favgw:red:5";
gpios = <&gpiofav 23 1>;
};
port_26 {
label = "favgw:red:6";
gpios = <&gpiofav 22 1>;
};
port_25 {
label = "favgw:red:7";
gpios = <&gpiofav 21 1>;
};
port_24 {
label = "favgw:red:8";
gpios = <&gpiofav 20 1>;
};
port_23 {
label = "favgw:green:1";
gpios = <&gpiofav 19 1>;
};
port_22 {
label = "favgw:green:2";
gpios = <&gpiofav 18 1>;
};
port_21 {
label = "favgw:green:3";
gpios = <&gpiofav 17 1>;
};
port_20 {
label = "favgw:green:4";
gpios = <&gpiofav 16 1>;
};
port_19 {
label = "favgw:green:5";
gpios = <&gpiofav 15 1>;
};
port_18 {
label = "favgw:green:6";
gpios = <&gpiofav 14 1>;
};
port_17 {
label = "favgw:green:7";
gpios = <&gpiofav 13 1>;
};
port_16 {
label = "favgw:green:8";
gpios = <&gpiofav 12 1>;
};
port_15 {
label = "favgw:yellow:9";
gpios = <&gpiofav 11 1>;
};
port_14 {
label = "favgw:yellow:10";
gpios = <&gpiofav 10 1>;
};
port_13 {
label = "favgw:yellow:11";
gpios = <&gpiofav 9 1>;
};
port_12 {
label = "favgw:yellow:12";
gpios = <&gpiofav 8 1>;
};
port_11 {
label = "favgw:yellow:13";
gpios = <&gpiofav 7 1>;
};
port_10 {
label = "favgw:yellow:14";
gpios = <&gpiofav 6 1>;
};
port_9 {
label = "favgw:yellow:15";
gpios = <&gpiofav 5 1>;
};
port_8 {
label = "favgw:yellow:16";
gpios = <&gpiofav 4 1>;
};
};
};

/* crypto@20000 {
compatible = "fsl,sec1.2", "fsl,sec1.0";
reg = <0x20000 0x8000>;
interrupts = <1 1>;
interrupt-parent = <&PIC>;
fsl,num-channels = <1>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x4c>;
fsl,descriptor-types-mask = <0x05000155>;
};
*/ };

chosen {
linux,stdout-path = &smc1;
};
};

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

Next message: Peter Zijlstra: "[PATCH] trace: Robustify wait loop"
Previous message: Steinar H. Gunderson: "Re: bisected: futex regression >= 3.14 - was - Slowdown due to threads bouncing between HT cores"
Next in thread: Scott Wood: "Re: [PATCH 2/2] spi: fsl-spi: Allow dynamic allocation of CPM1 parameter RAM"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]