Re: [PATCH v5 12/20] x86: perf: intel_pt: Intel PT PMU driver

[Alexander Shishkin]

Peter Zijlstra <peterz@xxxxxxxxxxxxx> writes:

> On Mon, Oct 13, 2014 at 04:45:40PM +0300, Alexander Shishkin wrote:
>> +static int pt_config(struct perf_event *event)
>> +{
>> +	u64 reg;
>> +
>> +	reg = RTIT_CTL_TOPA | RTIT_CTL_BRANCH_EN;
>> +
>> +	if (!event->attr.exclude_kernel)
>> +		reg |= RTIT_CTL_OS;
>> +	if (!event->attr.exclude_user)
>> +		reg |= RTIT_CTL_USR;
>> +
>> +	reg |= (event->attr.config & PT_CONFIG_MASK);
>> +
>> +	/*
>> +	 * User can try to set bits in RTIT_CTL through PT_BYPASS_MASK,
>> +	 * that aren't supported by the hardware. Weather or not a
>> +	 * particular bitmask is supported by a cpu can't be determined
>> +	 * via cpuid or otherwise, so we have to rely on #GP handling
>> +	 * to catch these cases.
>> +	 */
>> +	return wrmsrl_safe(MSR_IA32_RTIT_CTL, reg);
>> +}
>
> Whether the weather is nice or not :-)
>
> But no, this cannot be, once we've accepted the event is must be
> programmable. Failing at the time of programming is vile; pmu::start()
> is a void return, failure is not an option there.

This is called from pmu::add(), which can fail. If this wrmsrl throws a
gp, pmu::add() will fail and we won't even get to pmu::start(). Of
course, the problem with such event faulting every time it is added is
still there. Maybe we can simply disable such events after the first
fault. Good news is, only a CAP_SYS_ADMIN can set arbitrary bits, so the
damage is limited.

> The fact that the hardware cannot even tell you the supported mask is
> further fail.
>
> IIRC I think Andi once suggested probing each of the 64 bits in that MSR
> to determine the supported mask at device init time.

The problem with this is that some bits go in groups, there'd be 2..3..4
bit fields encoding desired packet frequency, for example.

Regards,
--
Alex
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