linux-next: manual merge of the idle tree with the pm tree

[Stephen Rothwell]

Hi Len,

Today's linux-next merge of the idle tree got a conflict in
arch/x86/include/uapi/asm/msr-index.h between commit 2f86dc4cddcb
("intel_pstate: Add support for HWP") from the pm tree and commit
a8b65b07d753 ("tools/power turbostat: decode MSR_*_PERF_LIMIT_REASONS")
from the idle tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@xxxxxxxxxxxxxxxx

diff --cc arch/x86/include/uapi/asm/msr-index.h
index 62838e54947d,c1cb18be540e..000000000000
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@@ -149,48 -149,10 +149,52 @@@
  
  #define MSR_CORE_C1_RES			0x00000660
  
 +#define MSR_CC6_DEMOTION_POLICY_CONFIG	0x00000668
 +#define MSR_MC6_DEMOTION_POLICY_CONFIG	0x00000669
 +
 +/* Hardware P state interface */
 +#define MSR_PPERF			0x0000064e
 +#define MSR_PERF_LIMIT_REASONS		0x0000064f
 +#define MSR_PM_ENABLE			0x00000770
 +#define MSR_HWP_CAPABILITIES		0x00000771
 +#define MSR_HWP_REQUEST_PKG		0x00000772
 +#define MSR_HWP_INTERRUPT		0x00000773
 +#define MSR_HWP_REQUEST 		0x00000774
 +#define MSR_HWP_STATUS			0x00000777
 +
 +/* CPUID.6.EAX */
 +#define HWP_BASE_BIT			(1<<7)
 +#define HWP_NOTIFICATIONS_BIT		(1<<8)
 +#define HWP_ACTIVITY_WINDOW_BIT		(1<<9)
 +#define HWP_ENERGY_PERF_PREFERENCE_BIT	(1<<10)
 +#define HWP_PACKAGE_LEVEL_REQUEST_BIT	(1<<11)
 +
 +/* IA32_HWP_CAPABILITIES */
 +#define HWP_HIGHEST_PERF(x)		(x & 0xff)
 +#define HWP_GUARANTEED_PERF(x)		((x & (0xff << 8)) >>8)
 +#define HWP_MOSTEFFICIENT_PERF(x)	((x & (0xff << 16)) >>16)
 +#define HWP_LOWEST_PERF(x)		((x & (0xff << 24)) >>24)
 +
 +/* IA32_HWP_REQUEST */
 +#define HWP_MIN_PERF(x) 		(x & 0xff)
 +#define HWP_MAX_PERF(x) 		((x & 0xff) << 8)
 +#define HWP_DESIRED_PERF(x)		((x & 0xff) << 16)
 +#define HWP_ENERGY_PERF_PREFERENCE(x)	((x & 0xff) << 24)
 +#define HWP_ACTIVITY_WINDOW(x)		((x & 0xff3) << 32)
 +#define HWP_PACKAGE_CONTROL(x)		((x & 0x1) << 42)
 +
 +/* IA32_HWP_STATUS */
 +#define HWP_GUARANTEED_CHANGE(x)	(x & 0x1)
 +#define HWP_EXCURSION_TO_MINIMUM(x)	(x & 0x4)
 +
 +/* IA32_HWP_INTERRUPT */
 +#define HWP_CHANGE_TO_GUARANTEED_INT(x)	(x & 0x1)
 +#define HWP_EXCURSION_TO_MINIMUM_INT(x)	(x & 0x2)
 +
+ #define MSR_CORE_PERF_LIMIT_REASONS	0x00000690
+ #define MSR_GFX_PERF_LIMIT_REASONS	0x000006B0
+ #define MSR_RING_PERF_LIMIT_REASONS	0x000006B1
+ 
  #define MSR_AMD64_MC0_MASK		0xc0010044
  
  #define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))

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