[PATCH] ARM: vfp: Silence mvfr0 unused variable warning
From: Stephen Boyd
Date: Tue Nov 18 2014 - 15:56:41 EST
Stephen Rothwell reports that commit 3f4c9f8f0a20 ("ARM: 8197/1:
vfp: Fix VFPv3 hwcap detection on CPUID based cpus") introduced an
unused variable warning.
arch/arm/vfp/vfpmodule.c: In function 'vfp_init':
arch/arm/vfp/vfpmodule.c:725:6: warning: unused variable 'mvfr0'
[-Wunused-variable]
u32 mvfr0;
Silence this warning by using IS_ENABLED instead of ifdefs.
Reported-by: Stephen Rothwell <sfr@xxxxxxxxxxxxxxxx>
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
---
If you apply and use git show -b you can see that most of the diff
is indentation.
arch/arm/vfp/vfpmodule.c | 44 ++++++++++++++++++++++----------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 5002d002f6e3..216cd78f64aa 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -752,30 +752,30 @@ static int __init vfp_init(void)
* precision floating point operations. Only check
* for NEON if the hardware has the MVFR registers.
*/
-#ifdef CONFIG_NEON
- if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
+ if (IS_ENABLED(CONFIG_NEON) &&
+ (fmrx(MVFR1) & 0x000fff00) == 0x00011100)
elf_hwcap |= HWCAP_NEON;
-#endif
-#ifdef CONFIG_VFPv3
- mvfr0 = fmrx(MVFR0);
- if (((mvfr0 & MVFR0_DP_MASK) >> MVFR0_DP_BIT) == 0x2 ||
- ((mvfr0 & MVFR0_SP_MASK) >> MVFR0_SP_BIT) == 0x2) {
- elf_hwcap |= HWCAP_VFPv3;
- /*
- * Check for VFPv3 D16 and VFPv4 D16. CPUs in
- * this configuration only have 16 x 64bit
- * registers.
- */
- if ((mvfr0 & MVFR0_A_SIMD_MASK) == 1)
- /* also v4-D16 */
- elf_hwcap |= HWCAP_VFPv3D16;
- else
- elf_hwcap |= HWCAP_VFPD32;
- }
- if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
- elf_hwcap |= HWCAP_VFPv4;
-#endif
+ if (IS_ENABLED(CONFIG_VFPv3)) {
+ mvfr0 = fmrx(MVFR0);
+ if (((mvfr0 & MVFR0_DP_MASK) >> MVFR0_DP_BIT) == 0x2 ||
+ ((mvfr0 & MVFR0_SP_MASK) >> MVFR0_SP_BIT) == 0x2) {
+ elf_hwcap |= HWCAP_VFPv3;
+ /*
+ * Check for VFPv3 D16 and VFPv4 D16. CPUs in
+ * this configuration only have 16 x 64bit
+ * registers.
+ */
+ if ((mvfr0 & MVFR0_A_SIMD_MASK) == 1)
+ /* also v4-D16 */
+ elf_hwcap |= HWCAP_VFPv3D16;
+ else
+ elf_hwcap |= HWCAP_VFPD32;
+ }
+
+ if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
+ elf_hwcap |= HWCAP_VFPv4;
+ }
/* Extract the architecture version on pre-cpuid scheme */
} else {
if (vfpsid & FPSID_NODOUBLE) {
--
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