[PATCH 05/15] dt: binding: add binding for TZ1090 gate bank

[James Hogan]

Add DT binding for a bank of clock gates in the TZ1090 SoC. There are
several such registers which contain only bits controlling clock gates.

The bit-mask property determines the mask of bits of the register which
control gates. The number of input (and output) clocks is equal to the
number of set bits in the bit-mask, and the clocks and
clock-output-names arrays list the clocks/names from the least
significant set bit in the mask to the most significant set bit.

Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
Cc: Mike Turquette <mturquette@xxxxxxxxxx>
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Pawel Moll <pawel.moll@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: Ian Campbell <ijc+devicetree@xxxxxxxxxxxxxx>
Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
Cc: linux-metag@xxxxxxxxxxxxxxx
Cc: devicetree@xxxxxxxxxxxxxxx
---
 .../bindings/clock/img,tz1090-gate-bank.txt        | 52 ++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/img,tz1090-gate-bank.txt

diff --git a/Documentation/devicetree/bindings/clock/img,tz1090-gate-bank.txt b/Documentation/devicetree/bindings/clock/img,tz1090-gate-bank.txt
new file mode 100644
index 0000000..7a93f6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,tz1090-gate-bank.txt
@@ -0,0 +1,52 @@
+Binding for TZ1090 clock gate bank.
+
+This binding uses the common clock binding[1]. It assumes a register-mapped bank
+of clock gates, where each bit in the register can control a single gate. The
+number of clocks in the bank is specified indirectly by the number of set bits
+in the bit-mask property.
+
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible         : shall be "img,tz1090-gate-bank".
+- #clock-cells       : from common clock binding; shall be set to 1.
+- reg                : base address for register controlling gates
+- bit-mask           : bitmask of bits in register controlling gates
+- clocks             : clock specifiers of parent clock of each gate with bit
+                       set in bit-mask
+- clock-output-names : from common clock binding. Name of each gate with bit set
+                       in bit-mask
+
+Clock Specifier Definition:
+- <1st-cell>: gate number, counting from 0 (the gate controlled by the lowest
+              set bit in bit-mask) to the number of gates - 1 (i.e.  omitting
+              any clear bits in bit-mask)
+
+Examples:
+	clkenab {
+		compatible = "img,tz1090-gate-bank";
+		#clock-cells = <1>;
+		reg = <0x0200590c 0x4>;
+		bit-mask = <0x020b7220>;
+		clock-output-names =
+			"out0_en",
+			"out1_en",
+			"i2s_en",
+			"scb_en",
+			"uart_en",
+			"ext_stc1_en",
+			"ext_stc1_en",
+			"usb_en",
+			"adcpll_en";
+		clocks =
+			<&clkswitch 5>,
+			<&clkswitch 9>,
+			<&clkswitch 12>,
+			<&clkswitch 13>,
+			<&clkswitch 14>,
+			<&clkswitch 15>,
+			<&clkswitch 16>,
+			<&clkswitch 18>,
+			<&clkswitch 24>;
+	};
-- 
2.0.4

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