Re: [PATCH] ARM: pxa: fix lubbock interrupts handling
From: Robert Jarzmik
Date: Fri Nov 28 2014 - 08:30:19 EST
Thomas Gleixner <tglx@xxxxxxxxxxxxx> writes:
> So what is the relationship between installing that chained handler
> and that gpio-pxa probe stuff?
The relation is in gpio-pxa probe, look at the extract of pxa_gpio_probe() :
pxa_gpio_probe()
irq = gpio_to_irq(0);
irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
Now look at the extract from the former lubbock_init_irq() :
lubbock_init_irq()
irq = PXA_GPIO_TO_IRQ(0);
irq_set_chained_handler(irq, lubbock_irq_handler);
irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
Given that gpio_to_irq(0) = PXA_GPIO_TO_IRQ(0), see how these 2 are fighting to
install the handler, and how the resulting installed handler depends on the
order of execution of pxa_gpio_to_irq() wrt lubbock_init_irq().
> And why is the GPIO0 interrupt handled from arch code rather than from
> a regular driver setup, which depends on the availablity of the GPIO
> driver?
Ah that's a good question. Maybe the answer is that there is no driver in this
case.
When I say "no driver", it's because this interrupt is a consequence of the
IO-Board (or motherboard) wiring topology.
I think I need to add a bit of context, so pardon my crude ascii-art style, and
see in the lubbock case, we have this wiring (list of IPs not exhaustive, and
gates to mask each XXX irq not added) :
IPs on Motherboard Gates on motherboard SoC
+-------------+ +-------+
| SMC Lan | --lan irq--- | Latch | -
+-------------+ | | \ +------PXA-----+
| | \ | |
+-------------+ | | |+----------+ |
| UDC Vbus | --vbus irq-- | Latch | -- NOR gate -- GPIO0 -- ||GPIO block| |
+-------------+ | | line |+----------+ |
| | / | |
+-------------+ | | / +--------------+
| SA1111 | --sa11x irq--| Latch | -
+-------------+ +-------+
The "gates on motherboard" is what lubbock.c is describing, ie. the
interconnection on the motherboard. I don't see the device/driver model fitting
to describe these gates, do you ?
Cheers.
--
Robert
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