Re: [tip:x86/apic] x86, irq: Use cached IOAPIC entry instead of reading from hardware

[Jiang Liu]

On 2014/11/28 23:40, Jiang Liu wrote:
> On 2014/11/28 19:53, Borislav Petkov wrote:
>> On Fri, Nov 28, 2014 at 12:33:58PM +0100, Borislav Petkov wrote:
>>> On Fri, Nov 28, 2014 at 10:31:44AM +0800, Jiang Liu wrote:
>>>> 	Thanks for tracking down to this line of change. I have no
>>>> platform to reproduce this bug, so could you please help to revert this
>>>> commit and apply following patch to get some data about IOAPIC entry?
>>>
<snit>
>>
>> Ok, so this is interesting: the cached data has bit 16 set which,
>> AFAICT, is in one of those io redirection table registers. That bit
>> masks out interrupts and if set, those get ignored. Which would explain
>> the timeoutting of the ATA commands because the IRQ is masked.
>>
>> I don't know, though, why your cached data has bit 16 set....
> Hi Borislav,
> 	Sorry, my previous test patch has some issue, but I think I
> should have found the root cause now. Could you please try following
> patch directly on top of tip/master without reverting any patch?
Hi Borislav,
	With this patch applied, KVM with SMP kernel boots successfully
now:)
Regards!
Gerry

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