[PATCH 2/4] sh-pfc: Add emev2 pinmux support
From: Niklas SÃderlund
Date: Fri Dec 12 2014 - 15:11:36 EST
Add PFC support for the EMMA Mobile EV2 SoC including pin groups for
on-chip devices.
Signed-off-by: Niklas SÃderlund <niso@xxxxxx>
---
.../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
drivers/pinctrl/sh-pfc/Kconfig | 5 +
drivers/pinctrl/sh-pfc/Makefile | 1 +
drivers/pinctrl/sh-pfc/core.c | 9 +
drivers/pinctrl/sh-pfc/core.h | 1 +
drivers/pinctrl/sh-pfc/pfc-emev2.c | 1915 ++++++++++++++++++++
6 files changed, 1932 insertions(+)
create mode 100644 drivers/pinctrl/sh-pfc/pfc-emev2.c
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index daef6fa..b1b2a0a 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -10,6 +10,7 @@ Pin Control
Required Properties:
- compatible: should be one of the following.
+ - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
- "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
- "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
- "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 26187aa..3267e92 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -20,6 +20,11 @@ config GPIO_SH_PFC
This enables support for GPIOs within the SoC's pin function
controller.
+config PINCTRL_PFC_EMEV2
+ def_bool y
+ depends on ARCH_EMEV2
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A73A4
def_bool y
depends on ARCH_R8A73A4
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index ad8f4cf..b66432f 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
sh-pfc-objs += gpio.o
endif
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
+obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 6572c23..7e938b3 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -439,6 +439,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc)
#ifdef CONFIG_OF
static const struct of_device_id sh_pfc_of_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_EMEV2
+ {
+ .compatible = "renesas,pfc-emev2",
+ .data = &emev2_pinmux_info,
+ },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
{
.compatible = "renesas,pfc-r8a73a4",
@@ -579,6 +585,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
}
static const struct platform_device_id sh_pfc_id_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_EMEV2
+ { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 3daaa52..1998d13 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -65,6 +65,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
+extern const struct sh_pfc_soc_info emev2_pinmux_info;
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c
new file mode 100644
index 0000000..22c9e15
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c
@@ -0,0 +1,1915 @@
+/*
+ * Pin Function Controller Support
+ *
+ * Copyright (C) 2014 Niklas SÃderlund
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_32(0, fn, sfx), \
+ PORT_GP_32(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_32(3, fn, sfx), \
+ PORT_GP_32(4, fn, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA),
+ PINMUX_DATA_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN),
+
+ /* GPSR0 */
+ FN_LCD3_1_0_GP_0_18, FN_LCD3_1_0_GP_0_20, FN_LCD3_1_0_GP_0_21,
+ FN_LCD3_1_0_GP_0_22, FN_LCD3_1_0_GP_0_23,
+ FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB,
+
+ /* GPSR1 */
+ FN_LCD3_9_8_GP_1_6, FN_LCD3_9_8_GP_1_7, FN_LCD3_11_10_GP_1_8,
+ FN_LCD3_11_10_GP_1_9, FN_LCD3_11_10_GP_1_10, FN_LCD3_11_10_GP_1_11,
+ FN_IIC_1_0_GP_1_14, FN_IIC_1_0_GP_1_15,
+ FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5,
+ FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI,
+ FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2,
+ FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6,
+ FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD,
+
+ /* GPSR2 */
+ FN_AB_1_0_GP_2_7, FN_AB_1_0_GP_2_8, FN_AB_1_0_GP_2_9,
+ FN_AB_1_0_GP_2_10, FN_AB_1_0_GP_2_11, FN_AB_1_0_GP_2_12,
+ FN_AB_1_0_GP_2_13, FN_AB_1_0_GP_2_14, FN_AB_1_0_GP_2_15,
+ FN_AB_1_0_GP_2_16, FN_AB_1_0_GP_2_17, FN_AB_1_0_GP_2_18,
+ FN_AB_1_0_GP_2_19, FN_AB_1_0_GP_2_20, FN_AB_3_2_GP_2_21,
+ FN_AB_3_2_GP_2_22, FN_AB_3_2_GP_2_23, FN_AB_3_2_GP_2_24,
+ FN_AB_5_4_GP_2_25, FN_AB_5_4_GP_2_26, FN_AB_7_6_GP_2_27,
+ FN_AB_7_6_GP_2_28, FN_AB_1_0_GP_2_29, FN_AB_1_0_GP_2_30,
+ FN_AB_1_0_GP_2_31,
+ FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3,
+ FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1,
+
+ /* GPSR3 */
+ FN_AB_13_12_GP_3_8, FN_AB_13_12_GP_3_7, FN_AB_11_10_GP_3_6,
+ FN_AB_11_10_GP_3_5, FN_AB_11_10_GP_3_4, FN_AB_9_8_GP_3_3,
+ FN_AB_9_8_GP_3_2, FN_AB_9_8_GP_3_1,
+ FN_USI_1_0_GP_3_9, FN_USI_1_0_GP_3_10, FN_USI_1_0_GP_3_11,
+ FN_USI_1_0_GP_3_12, FN_USI_3_2_GP_3_13, FN_USI_3_2_GP_3_14,
+ FN_USI_5_4_GP_3_15, FN_USI_5_4_GP_3_16, FN_USI_5_4_GP_3_17,
+ FN_USI_5_4_GP_3_18, FN_USI_7_6_GP_3_19, FN_USI_9_8_GP_3_20,
+ FN_USI_9_8_GP_3_21,
+ FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI,
+ FN_USI1_DO,
+ FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2,
+ FN_NTSC_DATA3, FN_NTSC_DATA4,
+
+ /* GPRS4 */
+ FN_HSI_1_0_GP_4_15, FN_HSI_1_0_GP_4_16, FN_HSI_1_0_GP_4_17,
+ FN_HSI_1_0_GP_4_18, FN_HSI_1_0_GP_4_19, FN_HSI_1_0_GP_4_20,
+ FN_HSI_1_0_GP_4_21, FN_HSI_1_0_GP_4_22,
+ FN_UART_1_0_GP_4_29, FN_UART_1_0_GP_4_30,
+ FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO,
+ FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0,
+ FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4,
+ FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7,
+ FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX,
+ FN_UART1_TX,
+
+ /* CHG_PINSEL_LCD3 */
+ FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01,
+ FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10,
+ FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10,
+
+ /* CHG_PINSEL_IIC */
+ FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01,
+
+ /* CHG_PINSEL_AB */
+ FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00,
+ FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
+ FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10,
+ FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01,
+ FN_SEL_AB_7_6_10,
+ FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10,
+ FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10,
+ FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10,
+
+ /* CHG_PINSEL_USI */
+ FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01,
+ FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01,
+ FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01,
+ FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01,
+ FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01,
+
+ /* CHG_PINSEL_HSI */
+ FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01,
+
+ /* CHG_PINSEL_UART */
+ FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01,
+
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+
+ /* GPSR0 */
+ JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK,
+ LCD3_PXCLKB_MARK, SD_CKI_MARK,
+
+ /* GPSR1 */
+ LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK,
+ LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK,
+ SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK,
+ SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK,
+ SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK,
+ SDI1_CMD_MARK,
+
+ /* GPSR2 */
+ SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
+ AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK,
+
+ /* GPSR3 */
+ AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK,
+ USI1_DO_MARK,
+ NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK,
+ NTSC_DATA3_MARK, NTSC_DATA4_MARK,
+
+ /* GPSR3 */
+ NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK,
+ CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK,
+ CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK,
+ CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
+ JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK,
+ UART1_RX_MARK, UART1_TX_MARK,
+
+ /* CHG_PINSEL_LCD3 */
+ LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK,
+ LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK,
+ LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK,
+ LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
+ LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
+ YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK,
+ YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
+ YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK,
+ YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK,
+ YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
+ TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK,
+ TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK,
+ TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK,
+ TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK,
+ TP33_DATA14_MARK, TP33_DATA15_MARK,
+
+ /* CHG_PINSEL_IIC */
+ IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK,
+
+ /* CHG_PINSEL_AB */
+ AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK,
+ AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK,
+ AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK,
+ AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK,
+ AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK,
+ AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK,
+ AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK,
+ AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK,
+ AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK,
+ DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK,
+ DTV_DATA_A_MARK,
+ SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
+ SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK,
+ SDI2_DATA3_MARK,
+ CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK,
+ CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK,
+ CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
+ CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
+ CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
+ CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
+ CF_A00_MARK, CF_A01_MARK, CF_A02_MARK,
+ CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK,
+ USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
+ USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK,
+
+ /* CHG_PINSEL_USI */
+ USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK,
+ USI0_CS6_MARK,
+ USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
+ USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK,
+ USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
+ USI3_CS0_MARK,
+ USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
+ USI4_CS0_MARK, USI4_CS1_MARK,
+ PWM0_MARK, PWM1_MARK,
+ DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK,
+ DTV_DATA_B_MARK,
+
+ /* CHG_PINSEL_HSI */
+ HSI_CAWAKE_MARK, HSI_CADATA_MARK, HSI_CAFLAG_MARK,
+ HSI_ACREADY_MARK, HSI_ACWAKE_MARK, HSI_ACDATA_MARK,
+ HSI_ACFLAG_MARK, HSI_CAREADY_MARK, USI5_CLK_B_MARK,
+ USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK,
+ USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK,
+ USI5_DI_B_MARK,
+
+ /* CHG_PINSEL_UART */
+ UART1_CTSB_MARK, UART1_RTSB_MARK,
+ UART2_RX_MARK, UART2_TX_MARK,
+
+ PINMUX_MARK_END,
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers. */
+#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+ PINMUX_GPIO_GP_ALL(),
+
+ /* Pins not associated with a GPIO port */
+ SH_PFC_PIN_NAMED(2, 14, B14),
+ SH_PFC_PIN_NAMED(2, 15, B15),
+ SH_PFC_PIN_NAMED(2, 16, B16),
+ SH_PFC_PIN_NAMED(2, 17, B17),
+ SH_PFC_PIN_NAMED(3, 14, C14),
+ SH_PFC_PIN_NAMED(3, 15, C15),
+ SH_PFC_PIN_NAMED(3, 16, C16),
+ SH_PFC_PIN_NAMED(3, 17, C17),
+ SH_PFC_PIN_NAMED(4, 14, D14),
+ SH_PFC_PIN_NAMED(4, 15, D15),
+ SH_PFC_PIN_NAMED(4, 16, D16),
+ SH_PFC_PIN_NAMED(4, 17, D17),
+};
+
+static const u16 pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ /* GPSR0 */
+ /* V9 */
+ PINMUX_DATA(JT_SEL_MARK, FN_JT_SEL),
+ /* U9 */
+ PINMUX_DATA(ERR_RST_REQB_MARK, FN_ERR_RST_REQB),
+ /* V8 */
+ PINMUX_DATA(REF_CLKO_MARK, FN_REF_CLKO),
+ /* U8 */
+ PINMUX_DATA(EXT_CLKI_MARK, FN_EXT_CLKI),
+ /* B22*/
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_18, LCD3_PXCLK, SEL_LCD3_1_0_00),
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_18, YUV3_CLK_O, SEL_LCD3_1_0_01),
+ /* C21 */
+ PINMUX_DATA(LCD3_PXCLKB_MARK, FN_LCD3_PXCLKB),
+ /* A21 */
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_20, LCD3_CLK_I, SEL_LCD3_1_0_00),
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_20, YUV3_CLK_I, SEL_LCD3_1_0_01),
+ /* B21 */
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_21, LCD3_HS, SEL_LCD3_1_0_00),
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_21, YUV3_HS, SEL_LCD3_1_0_01),
+ /* C20 */
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_22, LCD3_VS, SEL_LCD3_1_0_00),
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_22, YUV3_VS, SEL_LCD3_1_0_01),
+ /* D19 */
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_23, LCD3_DE, SEL_LCD3_1_0_00),
+ PINMUX_IPSR_NOFN(LCD3_1_0_GP_0_23, YUV3_DE, SEL_LCD3_1_0_01),
+
+ /* GPSR1 */
+ /* A20 */
+ PINMUX_DATA(LCD3_R0_MARK, FN_LCD3_R0),
+ /* B20 */
+ PINMUX_DATA(LCD3_R1_MARK, FN_LCD3_R1),
+ /* A19 */
+ PINMUX_DATA(LCD3_R2_MARK, FN_LCD3_R2),
+ /* B19 */
+ PINMUX_DATA(LCD3_R3_MARK, FN_LCD3_R3),
+ /* C19 */
+ PINMUX_DATA(LCD3_R4_MARK, FN_LCD3_R4),
+ /* B18 */
+ PINMUX_DATA(LCD3_R5_MARK, FN_LCD3_R5),
+ /* C18 */
+ PINMUX_IPSR_NOFN(LCD3_9_8_GP_1_6, LCD3_R6, SEL_LCD3_9_8_00),
+ PINMUX_IPSR_NOFN(LCD3_9_8_GP_1_6, TP33_CLK, SEL_LCD3_9_8_10),
+ /* D18 */
+ PINMUX_IPSR_NOFN(LCD3_9_8_GP_1_7, LCD3_R7, SEL_LCD3_9_8_00),
+ PINMUX_IPSR_NOFN(LCD3_9_8_GP_1_7, TP33_CTRL, SEL_LCD3_9_8_10),
+ /* A18 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_8, LCD3_G0, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_8, YUV3_D0, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_8, TP33_DATA0, SEL_LCD3_11_10_10),
+ /* A17 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_9, LCD3_G1, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_9, YUV3_D1, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_9, TP33_DATA1, SEL_LCD3_11_10_10),
+ /* B17 */
+ PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00),
+ PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01),
+ PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10),
+ /* C17 */
+ PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00),
+ PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01),
+ PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10),
+ /* D17 */
+ PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00),
+ PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01),
+ PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10),
+ /* B16 */
+ PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00),
+ PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01),
+ PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10),
+ /* C16 */
+ PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00),
+ PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01),
+ PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10),
+ /* D16 */
+ PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00),
+ PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01),
+ PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10),
+ /* A16 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_10, LCD3_B0, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_10, YUV3_D8, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_10, TP33_DATA8, SEL_LCD3_11_10_10),
+ /* A15 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, LCD3_B1, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, YUV3_D9, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, TP33_DATA9, SEL_LCD3_11_10_10),
+ /* B15 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, LCD3_B2, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, YUV3_D10, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, TP33_DATA10, SEL_LCD3_11_10_10),
+ /* C15 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, LCD3_B3, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, YUV3_D11, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, TP33_DATA11, SEL_LCD3_11_10_10),
+ /* D15 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, LCD3_B4, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, YUV3_D12, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, TP33_DATA12, SEL_LCD3_11_10_10),
+ /* B14 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, LCD3_B5, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, YUV3_D13, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, TP33_DATA13, SEL_LCD3_11_10_10),
+ /* C14 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, LCD3_B6, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, YUV3_D14, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, TP33_DATA14, SEL_LCD3_11_10_10),
+ /* D14 */
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, LCD3_B7, SEL_LCD3_11_10_00),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, YUV3_D15, SEL_LCD3_11_10_01),
+ PINMUX_IPSR_NOFN(LCD3_11_10_GP_1_11, TP33_DATA15, SEL_LCD3_11_10_10),
+ /* AA9 */
+ PINMUX_DATA(IIC0_SCL_MARK, FN_IIC0_SCL),
+ /* AA8 */
+ PINMUX_DATA(IIC0_SDA_MARK, FN_IIC0_SDA),
+ /* Y9 */
+ PINMUX_IPSR_NOFN(IIC_1_0_GP_1_14, IIC1_SCL, SEL_IIC_1_0_00),
+ PINMUX_IPSR_NOFN(IIC_1_0_GP_1_14, UART3_RX, SEL_IIC_1_0_01),
+ /* Y8 */
+ PINMUX_IPSR_NOFN(IIC_1_0_GP_1_15, IIC1_SDA, SEL_IIC_1_0_00),
+ PINMUX_IPSR_NOFN(IIC_1_0_GP_1_15, UART3_TX, SEL_IIC_1_0_01),
+ /* AC19 */
+ PINMUX_DATA(SD_CKI_MARK, FN_SD_CKI),
+ /* AB18 */
+ PINMUX_DATA(SDI0_CKO_MARK, FN_SDI0_CKO),
+ /* AC18 */
+ PINMUX_DATA(SDI0_CKI_MARK, FN_SDI0_CKI),
+ /* Y12 */
+ PINMUX_DATA(SDI0_CMD_MARK, FN_SDI0_CMD),
+ /* AA13 */
+ PINMUX_DATA(SDI0_DATA0_MARK, FN_SDI0_DATA0),
+ /* Y13 */
+ PINMUX_DATA(SDI0_DATA1_MARK, FN_SDI0_DATA1),
+ /* AA14 */
+ PINMUX_DATA(SDI0_DATA2_MARK, FN_SDI0_DATA2),
+ /* Y14 */
+ PINMUX_DATA(SDI0_DATA3_MARK, FN_SDI0_DATA3),
+ /* AA15 */
+ PINMUX_DATA(SDI0_DATA4_MARK, FN_SDI0_DATA4),
+ /* Y15 */
+ PINMUX_DATA(SDI0_DATA5_MARK, FN_SDI0_DATA5),
+ /* AA16 */
+ PINMUX_DATA(SDI0_DATA6_MARK, FN_SDI0_DATA6),
+ /* Y16 */
+ PINMUX_DATA(SDI0_DATA7_MARK, FN_SDI0_DATA7),
+ /* AB22 */
+ PINMUX_DATA(SDI1_CKO_MARK, FN_SDI1_CKO),
+ /* AA23 */
+ PINMUX_DATA(SDI1_CKI_MARK, FN_SDI1_CKI),
+ /* AC21 */
+ PINMUX_DATA(SDI1_CMD_MARK, FN_SDI1_CMD),
+
+ /* GPSR2 */
+ /* AB21 */
+ PINMUX_DATA(SDI1_DATA0_MARK, FN_SDI1_DATA0),
+ /* AB20 */
+ PINMUX_DATA(SDI1_DATA1_MARK, FN_SDI1_DATA1),
+ /* AB19 */
+ PINMUX_DATA(SDI1_DATA2_MARK, FN_SDI1_DATA2),
+ /* AA19 */
+ PINMUX_DATA(SDI1_DATA3_MARK, FN_SDI1_DATA3),
+ /* J23 */
+ PINMUX_DATA(AB_CLK_MARK, FN_AB_CLK),
+ /* D21 */
+ PINMUX_DATA(AB_CSB0_MARK, FN_AB_CSB0),
+ /* E21 */
+ PINMUX_DATA(AB_CSB1_MARK, FN_AB_CSB1),
+ /* F20 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_7, AB_CSB2, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_7, CF_CSB0, SEL_AB_1_0_10),
+ /* G20 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_8, AB_CSB3, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_8, CF_CSB1, SEL_AB_1_0_10),
+ /* J20 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_9, AB_RDB, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_9, CF_IORDB, SEL_AB_1_0_10),
+ /* H20 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_10, AB_WRB, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_10, CF_IOWRB, SEL_AB_1_0_10),
+ /* L20 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_11, AB_WAIT, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_11, CF_IORDY, SEL_AB_1_0_10),
+ /* K20 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_12, AB_ADV, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_12, CF_RESET, SEL_AB_1_0_10),
+ /* C23 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_13, AB_AD0, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_13, CF_D00, SEL_AB_1_0_10),
+ /* C22 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_14, AB_AD1, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_14, CF_D01, SEL_AB_1_0_10),
+ /* D23 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_15, AB_AD2, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_15, CF_D02, SEL_AB_1_0_10),
+ /* D22 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_16, AB_AD3, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_16, CF_D03, SEL_AB_1_0_10),
+ /* E23 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_17, AB_AD4, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_17, CF_D04, SEL_AB_1_0_10),
+ /* E22 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_18, AB_AD5, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_18, CF_D05, SEL_AB_1_0_10),
+ /* F23 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_19, AB_AD6, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_19, CF_D06, SEL_AB_1_0_10),
+ /* F22 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_20, AB_AD7, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_20, CF_D07, SEL_AB_1_0_10),
+ /* F21 */
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_21, AB_AD8, SEL_AB_3_2_00),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_21, DTV_BCLK_A, SEL_AB_3_2_01),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_21, CF_D08, SEL_AB_3_2_10),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_21, USI5_CLK_A, SEL_AB_3_2_11),
+ /* G23 */
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_22, AB_AD9, SEL_AB_3_2_00),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_22, DTV_PSYNC_A, SEL_AB_3_2_01),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_22, CF_D09, SEL_AB_3_2_10),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_22, USI5_DI_A, SEL_AB_3_2_11),
+ /* G22 */
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_23, AB_AD10, SEL_AB_3_2_00),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_23, DTV_VALID_A, SEL_AB_3_2_01),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_23, CF_D10, SEL_AB_3_2_10),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_23, USI5_DO_A, SEL_AB_3_2_11),
+ /* G21 */
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_24, AB_AD11, SEL_AB_3_2_00),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_24, DTV_DATA_A, SEL_AB_3_2_01),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_24, CF_D11, SEL_AB_3_2_10),
+ PINMUX_IPSR_NOFN(AB_3_2_GP_2_24, USI5_CS0_A, SEL_AB_3_2_11),
+ /* H23 */
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_25, AB_AD12, SEL_AB_5_4_00),
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_25, SDI2_DATA0, SEL_AB_5_4_01),
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_25, CF_D12, SEL_AB_5_4_10),
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_25, USI5_CS1_A, SEL_AB_5_4_11),
+ /* H22 */
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_26, AB_AD13, SEL_AB_5_4_00),
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_26, SDI2_DATA1, SEL_AB_5_4_01),
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_26, CF_D13, SEL_AB_5_4_10),
+ PINMUX_IPSR_NOFN(AB_5_4_GP_2_26, USI5_CS2_A, SEL_AB_5_4_11),
+ /* H21 */
+ PINMUX_IPSR_NOFN(AB_7_6_GP_2_27, AB_AD14, SEL_AB_7_6_00),
+ PINMUX_IPSR_NOFN(AB_7_6_GP_2_27, SDI2_DATA2, SEL_AB_7_6_01),
+ PINMUX_IPSR_NOFN(AB_7_6_GP_2_27, CF_D14, SEL_AB_7_6_10),
+ /* J22 */
+ PINMUX_IPSR_NOFN(AB_7_6_GP_2_28, AB_AD15, SEL_AB_7_6_00),
+ PINMUX_IPSR_NOFN(AB_7_6_GP_2_28, SDI2_DATA3, SEL_AB_7_6_01),
+ PINMUX_IPSR_NOFN(AB_7_6_GP_2_28, CF_D15, SEL_AB_7_6_10),
+ /* J21 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_29, AB_A17, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_29, CF_A00, SEL_AB_1_0_10),
+ /* K21 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_30, AB_A18, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_30, CF_A01, SEL_AB_1_0_10),
+ /* L21 */
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_31, AB_A19, SEL_AB_1_0_00),
+ PINMUX_IPSR_NOFN(AB_1_0_GP_2_31, CF_A02, SEL_AB_1_0_10),
+
+ /* GPSR3 */
+ /* M21 */
+ PINMUX_DATA(AB_A20_MARK, FN_AB_A20),
+ /* N21 */
+ PINMUX_IPSR_NOFN(AB_9_8_GP_3_1, AB_A21, SEL_AB_9_8_00),
+ PINMUX_IPSR_NOFN(AB_9_8_GP_3_1, SDI2_CKO, SEL_AB_9_8_01),
+ PINMUX_IPSR_NOFN(AB_9_8_GP_3_1, CF_INTRQ, SEL_AB_9_8_10),
+ /* M20 */
+ PINMUX_IPSR_NOFN(AB_9_8_GP_3_2, AB_A22, SEL_AB_9_8_00),
+ PINMUX_IPSR_NOFN(AB_9_8_GP_3_2, SDI2_CKI, SEL_AB_9_8_01),
+ /* N20 */
+ PINMUX_IPSR_NOFN(AB_9_8_GP_3_3, AB_A23, SEL_AB_9_8_00),
+ PINMUX_IPSR_NOFN(AB_9_8_GP_3_3, SDI2_CMD, SEL_AB_9_8_01),
+ /* L18 */
+ PINMUX_IPSR_NOFN(AB_11_10_GP_3_4, AB_A24, SEL_AB_11_10_00),
+ PINMUX_IPSR_NOFN(AB_11_10_GP_3_4, CF_INPACKB, SEL_AB_11_10_10),
+ /* M18 */
+ PINMUX_IPSR_NOFN(AB_11_10_GP_3_5, AB_A25, SEL_AB_11_10_00),
+ PINMUX_IPSR_NOFN(AB_11_10_GP_3_5, CF_CDB1, SEL_AB_11_10_10),
+ /* N18 */
+ PINMUX_IPSR_NOFN(AB_11_10_GP_3_6, AB_A26, SEL_AB_11_10_00),
+ PINMUX_IPSR_NOFN(AB_11_10_GP_3_6, CF_CDB2, SEL_AB_11_10_10),
+ /* L17 */
+ PINMUX_IPSR_NOFN(AB_13_12_GP_3_7, AB_A27, SEL_AB_13_12_00),
+ PINMUX_IPSR_NOFN(AB_13_12_GP_3_7, AB_BEN0, SEL_AB_13_12_10),
+ /* M17 */
+ PINMUX_IPSR_NOFN(AB_13_12_GP_3_8, AB_A28, SEL_AB_13_12_00),
+ PINMUX_IPSR_NOFN(AB_13_12_GP_3_8, AB_BEN1, SEL_AB_13_12_10),
+ /* B8 */
+ PINMUX_DATA(USI0_CS1_MARK, FN_USI0_CS1),
+ /* B9 */
+ PINMUX_DATA(USI0_CS2_MARK, FN_USI0_CS2),
+ /* C10 */
+ PINMUX_DATA(USI1_DI_MARK, FN_USI1_DI),
+ /* D10 */
+ PINMUX_DATA(USI1_DO_MARK, FN_USI1_DO),
+ /* AB5 */
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_9, USI2_CLK, SEL_USI_1_0_00),
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_9, DTV_BCLK_B, SEL_USI_1_0_01),
+ /* AA6 */
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_10, USI2_DI, SEL_USI_1_0_00),
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_10, DTV_PSYNC_B, SEL_USI_1_0_01),
+ /* AA5 */
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_11, USI2_DO, SEL_USI_1_0_00),
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_11, DTV_VALID_B, SEL_USI_1_0_01),
+ /* Y7 */
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_12, USI2_CS0, SEL_USI_1_0_00),
+ PINMUX_IPSR_NOFN(USI_1_0_GP_3_12, DTV_DATA_B, SEL_USI_1_0_01),
+ /* AA7 */
+ PINMUX_IPSR_NOFN(USI_3_2_GP_3_13, USI2_CS1, SEL_USI_3_2_00),
+ PINMUX_IPSR_NOFN(USI_3_2_GP_3_13, USI4_CS0, SEL_USI_3_2_01),
+ /* Y6 */
+ PINMUX_IPSR_NOFN(USI_3_2_GP_3_14, USI2_CS2, SEL_USI_3_2_00),
+ PINMUX_IPSR_NOFN(USI_3_2_GP_3_14, USI4_CS1, SEL_USI_3_2_01),
+ /* AC5 */
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_15, USI3_CLK, SEL_USI_5_4_00),
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_15, USI0_CS3, SEL_USI_5_4_01),
+ /* AC4 */
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_16, USI3_DI, SEL_USI_5_4_00),
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_16, USI0_CS4, SEL_USI_5_4_01),
+ /* AC3 */
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_17, USI3_DO, SEL_USI_5_4_00),
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_17, USI0_CS5, SEL_USI_5_4_01),
+ /* AB4 */
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_18, USI3_CS0, SEL_USI_5_4_00),
+ PINMUX_IPSR_NOFN(USI_5_4_GP_3_18, USI0_CS6, SEL_USI_5_4_01),
+ /* AB3 */
+ PINMUX_IPSR_NOFN(USI_7_6_GP_3_19, USI4_CLK, SEL_USI_7_6_01),
+ /* AA4 */
+ PINMUX_IPSR_NOFN(USI_9_8_GP_3_20, PWM0, SEL_USI_9_8_00),
+ PINMUX_IPSR_NOFN(USI_9_8_GP_3_20, USI4_DI, SEL_USI_9_8_01),
+ /* Y5 */
+ PINMUX_IPSR_NOFN(USI_9_8_GP_3_21, PWM1, SEL_USI_9_8_00),
+ PINMUX_IPSR_NOFN(USI_9_8_GP_3_21, USI4_DO, SEL_USI_9_8_01),
+ /* V20 */
+ PINMUX_DATA(NTSC_CLK_MARK, FN_NTSC_CLK),
+ /* P20 */
+ PINMUX_DATA(NTSC_DATA0_MARK, FN_NTSC_DATA0),
+ /* P18 */
+ PINMUX_DATA(NTSC_DATA1_MARK, FN_NTSC_DATA1),
+ /* R20 */
+ PINMUX_DATA(NTSC_DATA2_MARK, FN_NTSC_DATA2),
+ /* R18 */
+ PINMUX_DATA(NTSC_DATA3_MARK, FN_NTSC_DATA3),
+ /* T20 */
+ PINMUX_DATA(NTSC_DATA4_MARK, FN_NTSC_DATA4),
+
+ /* GPRS3 */
+ /* T18 */
+ PINMUX_DATA(NTSC_DATA5_MARK, FN_NTSC_DATA5),
+ /* U20 */
+ PINMUX_DATA(NTSC_DATA6_MARK, FN_NTSC_DATA6),
+ /* U18 */
+ PINMUX_DATA(NTSC_DATA7_MARK, FN_NTSC_DATA7),
+ /* W23 */
+ PINMUX_DATA(CAM_CLKO_MARK, FN_CAM_CLKO),
+ /* Y23 */
+ PINMUX_DATA(CAM_CLKI_MARK, FN_CAM_CLKI),
+ /* W22 */
+ PINMUX_DATA(CAM_VS_MARK, FN_CAM_VS),
+ /* V21 */
+ PINMUX_DATA(CAM_HS_MARK, FN_CAM_HS),
+ /* T21 */
+ PINMUX_DATA(CAM_YUV0_MARK, FN_CAM_YUV0),
+ /* T22 */
+ PINMUX_DATA(CAM_YUV1_MARK, FN_CAM_YUV1),
+ /* T23 */
+ PINMUX_DATA(CAM_YUV2_MARK, FN_CAM_YUV2),
+ /* U21 */
+ PINMUX_DATA(CAM_YUV3_MARK, FN_CAM_YUV3),
+ /* U22 */
+ PINMUX_DATA(CAM_YUV4_MARK, FN_CAM_YUV4),
+ /* U23 */
+ PINMUX_DATA(CAM_YUV5_MARK, FN_CAM_YUV5),
+ /* V22 */
+ PINMUX_DATA(CAM_YUV6_MARK, FN_CAM_YUV6),
+ /* V23 */
+ PINMUX_DATA(CAM_YUV7_MARK, FN_CAM_YUV7),
+ /* K22 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_15, HSI_CAWAKE, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_15, USI5_CLK_B, SEL_HSI_1_0_01),
+ /* K23 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_16, HSI_CADATA, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_16, USI5_DO_B, SEL_HSI_1_0_01),
+ /* L23 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_17, HSI_CAFLAG, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_17, USI5_CS0_B, SEL_HSI_1_0_01),
+ /* L22 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_18, HSI_ACREADY, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_18, USI5_CS1_B, SEL_HSI_1_0_01),
+ /* N22 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_19, HSI_ACWAKE, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_19, USI5_CS2_B, SEL_HSI_1_0_01),
+ /* N23 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_20, HSI_ACDATA, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_20, USI5_CS3_B, SEL_HSI_1_0_01),
+ /* M23 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_21, HSI_ACFLAG, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_21, USI5_CS4_B, SEL_HSI_1_0_01),
+ /* M22 */
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_22, HSI_CAREADY, SEL_HSI_1_0_00),
+ PINMUX_IPSR_NOFN(HSI_1_0_GP_4_22, USI5_DI_B, SEL_HSI_1_0_01),
+ /* D13 */
+ PINMUX_DATA(JT_TDO_MARK, FN_JT_TDO),
+ /* F13 */
+ PINMUX_DATA(JT_TDOEN_MARK, FN_JT_TDOEN),
+ /* AA12 */
+ PINMUX_DATA(USB_VBUS_MARK, FN_USB_VBUS),
+ /* A12 */
+ PINMUX_DATA(LOWPWR_MARK, FN_LOWPWR),
+ /* Y11 */
+ PINMUX_DATA(UART1_RX_MARK, FN_UART1_RX),
+ /* Y10 */
+ PINMUX_DATA(UART1_TX_MARK, FN_UART1_TX),
+ /* AA10 */
+ PINMUX_IPSR_NOFN(UART_1_0_GP_4_29, UART1_CTSB, SEL_UART_1_0_00),
+ PINMUX_IPSR_NOFN(UART_1_0_GP_4_29, UART2_RX, SEL_UART_1_0_01),
+ /* AB10 */
+ PINMUX_IPSR_NOFN(UART_1_0_GP_4_30, UART1_RTSB, SEL_UART_1_0_00),
+ PINMUX_IPSR_NOFN(UART_1_0_GP_4_30, UART2_TX, SEL_UART_1_0_01),
+};
+
+
+#define EMEV_MUX_PIN(name, pin, mark) \
+ static const unsigned int name##_pins[] = { pin }; \
+ static const unsigned int name##_mux[] = { mark##_MARK }
+
+/* = [ System ] =========== */
+EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);
+EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);
+EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);
+EMEV_MUX_PIN(lowpwr, 154, LOWPWR);
+
+/* = [ JTAG ] ============= */
+EMEV_MUX_PIN(jt_sel, 2, JT_SEL);
+EMEV_MUX_PIN(jt_tdo, 151, JT_TDO);
+EMEV_MUX_PIN(jt_tdoen, 152, JT_TDOEN);
+
+/* = [ LCD ] ============== */
+EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK);
+EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB);
+EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I);
+EMEV_MUX_PIN(lcd3_hs, 21, LCD3_HS);
+EMEV_MUX_PIN(lcd3_vs, 22, LCD3_VS);
+EMEV_MUX_PIN(lcd3_de, 23, LCD3_DE);
+EMEV_MUX_PIN(lcd3_r0, 32, LCD3_R0);
+EMEV_MUX_PIN(lcd3_r1, 33, LCD3_R1);
+EMEV_MUX_PIN(lcd3_r2, 34, LCD3_R2);
+EMEV_MUX_PIN(lcd3_r3, 35, LCD3_R3);
+EMEV_MUX_PIN(lcd3_r4, 36, LCD3_R4);
+EMEV_MUX_PIN(lcd3_r5, 37, LCD3_R5);
+EMEV_MUX_PIN(lcd3_r6, 38, LCD3_R6);
+EMEV_MUX_PIN(lcd3_r7, 39, LCD3_R7);
+EMEV_MUX_PIN(lcd3_g0, 40, LCD3_G0);
+EMEV_MUX_PIN(lcd3_g1, 41, LCD3_G1);
+EMEV_MUX_PIN(lcd3_g2, PIN_NUMBER(2, 17), LCD3_G2);
+EMEV_MUX_PIN(lcd3_g3, PIN_NUMBER(3, 17), LCD3_G3);
+EMEV_MUX_PIN(lcd3_g4, PIN_NUMBER(4, 17), LCD3_G4);
+EMEV_MUX_PIN(lcd3_g5, PIN_NUMBER(2, 16), LCD3_G5);
+EMEV_MUX_PIN(lcd3_g6, PIN_NUMBER(3, 16), LCD3_G6);
+EMEV_MUX_PIN(lcd3_g7, PIN_NUMBER(4, 16), LCD3_G7);
+EMEV_MUX_PIN(lcd3_b0, 42, LCD3_B0);
+EMEV_MUX_PIN(lcd3_b1, 43, LCD3_B1);
+EMEV_MUX_PIN(lcd3_b2, PIN_NUMBER(2, 15), LCD3_B2);
+EMEV_MUX_PIN(lcd3_b3, PIN_NUMBER(3, 15), LCD3_B3);
+EMEV_MUX_PIN(lcd3_b4, PIN_NUMBER(4, 15), LCD3_B4);
+EMEV_MUX_PIN(lcd3_b5, PIN_NUMBER(2, 14), LCD3_B5);
+EMEV_MUX_PIN(lcd3_b6, PIN_NUMBER(3, 14), LCD3_B6);
+EMEV_MUX_PIN(lcd3_b7, PIN_NUMBER(4, 14), LCD3_B7);
+
+/* = [ YUV ] ============== */
+EMEV_MUX_PIN(yuv3_clk_o, 18, YUV3_CLK_O);
+EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I);
+EMEV_MUX_PIN(yuv3_hs, 21, YUV3_HS);
+EMEV_MUX_PIN(yuv3_vs, 22, YUV3_VS);
+EMEV_MUX_PIN(yuv3_de, 23, YUV3_DE);
+EMEV_MUX_PIN(yuv3_d0, 40, YUV3_D0);
+EMEV_MUX_PIN(yuv3_d1, 41, YUV3_D1);
+EMEV_MUX_PIN(yuv3_d2, PIN_NUMBER(2, 17), YUV3_D2);
+EMEV_MUX_PIN(yuv3_d3, PIN_NUMBER(3, 17), YUV3_D3);
+EMEV_MUX_PIN(yuv3_d4, PIN_NUMBER(4, 17), YUV3_D4);
+EMEV_MUX_PIN(yuv3_d5, PIN_NUMBER(2, 16), YUV3_D5);
+EMEV_MUX_PIN(yuv3_d6, PIN_NUMBER(3, 16), YUV3_D6);
+EMEV_MUX_PIN(yuv3_d7, PIN_NUMBER(4, 16), YUV3_D7);
+EMEV_MUX_PIN(yuv3_d8, 42, YUV3_D8);
+EMEV_MUX_PIN(yuv3_d9, 43, YUV3_D9);
+EMEV_MUX_PIN(yuv3_d10, PIN_NUMBER(2, 15), YUV3_D10);
+EMEV_MUX_PIN(yuv3_d11, PIN_NUMBER(3, 15), YUV3_D11);
+EMEV_MUX_PIN(yuv3_d12, PIN_NUMBER(4, 15), YUV3_D12);
+EMEV_MUX_PIN(yuv3_d13, PIN_NUMBER(2, 14), YUV3_D13);
+EMEV_MUX_PIN(yuv3_d14, PIN_NUMBER(3, 14), YUV3_D14);
+EMEV_MUX_PIN(yuv3_d15, PIN_NUMBER(4, 14), YUV3_D15);
+
+/* = [ TP33 ] ============= */
+EMEV_MUX_PIN(tp33_clk, 38, TP33_CLK);
+EMEV_MUX_PIN(tp33_ctrl, 39, TP33_CTRL);
+EMEV_MUX_PIN(tp33_data0, 40, TP33_DATA0);
+EMEV_MUX_PIN(tp33_data1, 41, TP33_DATA1);
+EMEV_MUX_PIN(tp33_data2, PIN_NUMBER(2, 17), TP33_DATA2);
+EMEV_MUX_PIN(tp33_data3, PIN_NUMBER(3, 17), TP33_DATA3);
+EMEV_MUX_PIN(tp33_data4, PIN_NUMBER(4, 17), TP33_DATA4);
+EMEV_MUX_PIN(tp33_data5, PIN_NUMBER(2, 16), TP33_DATA5);
+EMEV_MUX_PIN(tp33_data6, PIN_NUMBER(3, 16), TP33_DATA6);
+EMEV_MUX_PIN(tp33_data7, PIN_NUMBER(4, 16), TP33_DATA7);
+EMEV_MUX_PIN(tp33_data8, 42, TP33_DATA8);
+EMEV_MUX_PIN(tp33_data9, 43, TP33_DATA9);
+EMEV_MUX_PIN(tp33_data10, PIN_NUMBER(2, 15), TP33_DATA10);
+EMEV_MUX_PIN(tp33_data11, PIN_NUMBER(3, 15), TP33_DATA11);
+EMEV_MUX_PIN(tp33_data12, PIN_NUMBER(4, 15), TP33_DATA12);
+EMEV_MUX_PIN(tp33_data13, PIN_NUMBER(2, 14), TP33_DATA13);
+EMEV_MUX_PIN(tp33_data14, PIN_NUMBER(3, 14), TP33_DATA14);
+EMEV_MUX_PIN(tp33_data15, PIN_NUMBER(4, 14), TP33_DATA15);
+
+/* = [ IIC ] ============== */
+EMEV_MUX_PIN(iic0_scl, 44, IIC0_SCL);
+EMEV_MUX_PIN(iic0_sda, 45, IIC0_SDA);
+EMEV_MUX_PIN(iic1_scl, 46, IIC1_SCL);
+EMEV_MUX_PIN(iic1_sda, 47, IIC1_SDA);
+
+/* = [ UART ] ============= */
+EMEV_MUX_PIN(uart1_rx, 155, UART1_RX);
+EMEV_MUX_PIN(uart1_tx, 156, UART1_TX);
+EMEV_MUX_PIN(uart1_ctsb, 157, UART1_CTSB);
+EMEV_MUX_PIN(uart1_rtsb, 158, UART1_RTSB);
+EMEV_MUX_PIN(uart2_rx, 157, UART2_RX);
+EMEV_MUX_PIN(uart2_tx, 158, UART2_TX);
+EMEV_MUX_PIN(uart3_rx, 46, UART3_RX);
+EMEV_MUX_PIN(uart3_tx, 47, UART3_TX);
+
+/* = [ SD ] =============== */
+EMEV_MUX_PIN(sd_cki, 48, SD_CKI);
+
+/* = [ SDIO ] ============= */
+EMEV_MUX_PIN(sdi0_cko, 50, SDI0_CKO);
+EMEV_MUX_PIN(sdi0_cki, 51, SDI0_CKI);
+EMEV_MUX_PIN(sdi0_cmd, 52, SDI0_CMD);
+EMEV_MUX_PIN(sdi0_data0, 53, SDI0_DATA0);
+EMEV_MUX_PIN(sdi0_data1, 54, SDI0_DATA1);
+EMEV_MUX_PIN(sdi0_data2, 55, SDI0_DATA2);
+EMEV_MUX_PIN(sdi0_data3, 56, SDI0_DATA3);
+EMEV_MUX_PIN(sdi0_data4, 57, SDI0_DATA4);
+EMEV_MUX_PIN(sdi0_data5, 58, SDI0_DATA5);
+EMEV_MUX_PIN(sdi0_data6, 59, SDI0_DATA6);
+EMEV_MUX_PIN(sdi0_data7, 60, SDI0_DATA7);
+EMEV_MUX_PIN(sdi1_cko, 61, SDI1_CKO);
+EMEV_MUX_PIN(sdi1_cki, 62, SDI1_CKI);
+EMEV_MUX_PIN(sdi1_cmd, 63, SDI1_CMD);
+EMEV_MUX_PIN(sdi1_data0, 64, SDI1_DATA0);
+EMEV_MUX_PIN(sdi1_data1, 65, SDI1_DATA1);
+EMEV_MUX_PIN(sdi1_data2, 66, SDI1_DATA2);
+EMEV_MUX_PIN(sdi1_data3, 67, SDI1_DATA3);
+EMEV_MUX_PIN(sdi2_cko, 97, SDI2_CKO);
+EMEV_MUX_PIN(sdi2_cki, 98, SDI2_CKI);
+EMEV_MUX_PIN(sdi2_cmd, 99, SDI2_CMD);
+EMEV_MUX_PIN(sdi2_data0, 89, SDI2_DATA0);
+EMEV_MUX_PIN(sdi2_data1, 90, SDI2_DATA1);
+EMEV_MUX_PIN(sdi2_data2, 91, SDI2_DATA2);
+EMEV_MUX_PIN(sdi2_data3, 92, SDI2_DATA3);
+
+/* = [ External Memory] === */
+EMEV_MUX_PIN(ab_clk, 68, AB_CLK);
+EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0);
+EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1);
+EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2);
+EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3);
+EMEV_MUX_PIN(ab_rdb, 73, AB_RDB);
+EMEV_MUX_PIN(ab_wrb, 74, AB_WRB);
+EMEV_MUX_PIN(ab_wait, 75, AB_WAIT);
+EMEV_MUX_PIN(ab_adv, 76, AB_ADV);
+EMEV_MUX_PIN(ab_ad0, 77, AB_AD0);
+EMEV_MUX_PIN(ab_ad1, 78, AB_AD1);
+EMEV_MUX_PIN(ab_ad2, 79, AB_AD2);
+EMEV_MUX_PIN(ab_ad3, 80, AB_AD3);
+EMEV_MUX_PIN(ab_ad4, 81, AB_AD4);
+EMEV_MUX_PIN(ab_ad5, 82, AB_AD5);
+EMEV_MUX_PIN(ab_ad6, 83, AB_AD6);
+EMEV_MUX_PIN(ab_ad7, 84, AB_AD7);
+EMEV_MUX_PIN(ab_ad8, 85, AB_AD8);
+EMEV_MUX_PIN(ab_ad9, 86, AB_AD9);
+EMEV_MUX_PIN(ab_ad10, 87, AB_AD10);
+EMEV_MUX_PIN(ab_ad11, 88, AB_AD11);
+EMEV_MUX_PIN(ab_ad12, 89, AB_AD12);
+EMEV_MUX_PIN(ab_ad13, 90, AB_AD13);
+EMEV_MUX_PIN(ab_ad14, 91, AB_AD14);
+EMEV_MUX_PIN(ab_ad15, 92, AB_AD15);
+EMEV_MUX_PIN(ab_a17, 93, AB_A17);
+EMEV_MUX_PIN(ab_a18, 94, AB_A18);
+EMEV_MUX_PIN(ab_a19, 95, AB_A19);
+EMEV_MUX_PIN(ab_a20, 96, AB_A20);
+EMEV_MUX_PIN(ab_a21, 97, AB_A21);
+EMEV_MUX_PIN(ab_a22, 98, AB_A22);
+EMEV_MUX_PIN(ab_a23, 99, AB_A23);
+EMEV_MUX_PIN(ab_a24, 100, AB_A24);
+EMEV_MUX_PIN(ab_a25, 101, AB_A25);
+EMEV_MUX_PIN(ab_a26, 102, AB_A26);
+EMEV_MUX_PIN(ab_a27, 103, AB_A27);
+EMEV_MUX_PIN(ab_a28, 104, AB_A28);
+EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);
+EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);
+
+/* = [ DTV ] ============== */
+EMEV_MUX_PIN(dtv_bclk_a, 85, DTV_BCLK_A);
+EMEV_MUX_PIN(dtv_psync_a, 86, DTV_PSYNC_A);
+EMEV_MUX_PIN(dtv_valid_a, 87, DTV_VALID_A);
+EMEV_MUX_PIN(dtv_data_a, 88, DTV_DATA_A);
+EMEV_MUX_PIN(dtv_bclk_b, 115, DTV_BCLK_B);
+EMEV_MUX_PIN(dtv_psync_b, 116, DTV_PSYNC_B);
+EMEV_MUX_PIN(dtv_valid_b, 117, DTV_VALID_B);
+EMEV_MUX_PIN(dtv_data_b, 118, DTV_DATA_B);
+
+/* = [ CF ] -============== */
+EMEV_MUX_PIN(cf_csb0, 71, CF_CSB0);
+EMEV_MUX_PIN(cf_csb1, 72, CF_CSB1);
+EMEV_MUX_PIN(cf_iordb, 73, CF_IORDB);
+EMEV_MUX_PIN(cf_iowrb, 74, CF_IOWRB);
+EMEV_MUX_PIN(cf_iordy, 75, CF_IORDY);
+EMEV_MUX_PIN(cf_reset, 76, CF_RESET);
+EMEV_MUX_PIN(cf_d00, 77, CF_D00);
+EMEV_MUX_PIN(cf_d01, 78, CF_D01);
+EMEV_MUX_PIN(cf_d02, 79, CF_D02);
+EMEV_MUX_PIN(cf_d03, 80, CF_D03);
+EMEV_MUX_PIN(cf_d04, 81, CF_D04);
+EMEV_MUX_PIN(cf_d05, 82, CF_D05);
+EMEV_MUX_PIN(cf_d06, 83, CF_D06);
+EMEV_MUX_PIN(cf_d07, 84, CF_D07);
+EMEV_MUX_PIN(cf_d08, 85, CF_D08);
+EMEV_MUX_PIN(cf_d09, 86, CF_D09);
+EMEV_MUX_PIN(cf_d10, 87, CF_D10);
+EMEV_MUX_PIN(cf_d11, 88, CF_D11);
+EMEV_MUX_PIN(cf_d12, 89, CF_D12);
+EMEV_MUX_PIN(cf_d13, 90, CF_D13);
+EMEV_MUX_PIN(cf_d14, 91, CF_D14);
+EMEV_MUX_PIN(cf_d15, 92, CF_D15);
+EMEV_MUX_PIN(cf_a00, 93, CF_A00);
+EMEV_MUX_PIN(cf_a01, 94, CF_A01);
+EMEV_MUX_PIN(cf_a02, 95, CF_A02);
+EMEV_MUX_PIN(cf_intrq, 97, CF_INTRQ);
+EMEV_MUX_PIN(cf_inpackb, 100, CF_INPACKB);
+EMEV_MUX_PIN(cf_cdb1, 101, CF_CDB1);
+EMEV_MUX_PIN(cf_cdb2, 102, CF_CDB2);
+
+/* = [ USI ] ============== */
+EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);
+EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);
+EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);
+EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4);
+EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);
+EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);
+EMEV_MUX_PIN(usi1_di, 107, USI1_DI);
+EMEV_MUX_PIN(usi1_do, 108, USI1_DO);
+EMEV_MUX_PIN(usi2_clk, 109, USI2_CLK);
+EMEV_MUX_PIN(usi2_di, 110, USI2_DI);
+EMEV_MUX_PIN(usi2_do, 111, USI2_DO);
+EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0);
+EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1);
+EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2);
+EMEV_MUX_PIN(usi3_clk, 115, USI3_CLK);
+EMEV_MUX_PIN(usi3_di, 116, USI3_DI);
+EMEV_MUX_PIN(usi3_do, 117, USI3_DO);
+EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0);
+EMEV_MUX_PIN(usi4_clk, 119, USI4_CLK);
+EMEV_MUX_PIN(usi4_di, 120, USI4_DI);
+EMEV_MUX_PIN(usi4_do, 121, USI4_DO);
+EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0);
+EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1);
+EMEV_MUX_PIN(usi5_clk_a, 85, USI5_CLK_A);
+EMEV_MUX_PIN(usi5_di_a, 86, USI5_DI_A);
+EMEV_MUX_PIN(usi5_do_a, 87, USI5_DO_A);
+EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A);
+EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A);
+EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A);
+EMEV_MUX_PIN(usi5_clk_b, 143, USI5_CLK_B);
+EMEV_MUX_PIN(usi5_di_b, 144, USI5_DI_B);
+EMEV_MUX_PIN(usi5_do_b, 150, USI5_DO_B);
+EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B);
+EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B);
+EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B);
+EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B);
+EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B);
+
+/* = [ PWM ] ============== */
+EMEV_MUX_PIN(pwm0, 120, PWM0);
+EMEV_MUX_PIN(pwm1, 121, PWM1);
+
+/* = [ NTSC ] ============= */
+EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK);
+EMEV_MUX_PIN(ntsc_data0, 123, NTSC_DATA0);
+EMEV_MUX_PIN(ntsc_data1, 124, NTSC_DATA1);
+EMEV_MUX_PIN(ntsc_data2, 125, NTSC_DATA2);
+EMEV_MUX_PIN(ntsc_data3, 126, NTSC_DATA3);
+EMEV_MUX_PIN(ntsc_data4, 127, NTSC_DATA4);
+EMEV_MUX_PIN(ntsc_data5, 128, NTSC_DATA5);
+EMEV_MUX_PIN(ntsc_data6, 129, NTSC_DATA6);
+EMEV_MUX_PIN(ntsc_data7, 130, NTSC_DATA7);
+
+/* = [ CAM ] ============== */
+EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO);
+EMEV_MUX_PIN(cam_clki, 132, CAM_CLKI);
+EMEV_MUX_PIN(cam_vs, 133, CAM_VS);
+EMEV_MUX_PIN(cam_hs, 134, CAM_HS);
+EMEV_MUX_PIN(cam_yuv0, 135, CAM_YUV0);
+EMEV_MUX_PIN(cam_yuv1, 136, CAM_YUV1);
+EMEV_MUX_PIN(cam_yuv2, 137, CAM_YUV2);
+EMEV_MUX_PIN(cam_yuv3, 138, CAM_YUV3);
+EMEV_MUX_PIN(cam_yuv4, 139, CAM_YUV4);
+EMEV_MUX_PIN(cam_yuv5, 140, CAM_YUV5);
+EMEV_MUX_PIN(cam_yuv6, 141, CAM_YUV6);
+EMEV_MUX_PIN(cam_yuv7, 142, CAM_YUV7);
+
+/* = [ HSI ] ============== */
+EMEV_MUX_PIN(hsi_cawake, 143, HSI_CAWAKE);
+EMEV_MUX_PIN(hsi_cadata, 144, HSI_CADATA);
+EMEV_MUX_PIN(hsi_caflag, 145, HSI_CAFLAG);
+EMEV_MUX_PIN(hsi_acready, 146, HSI_ACREADY);
+EMEV_MUX_PIN(hsi_acwake, 147, HSI_ACWAKE);
+EMEV_MUX_PIN(hsi_acdata, 148, HSI_ACDATA);
+EMEV_MUX_PIN(hsi_acflag, 149, HSI_ACFLAG);
+EMEV_MUX_PIN(hsi_caready, 150, HSI_CAREADY);
+
+/* = [ USB ] ============== */
+EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS);
+
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(err_rst_reqb),
+ SH_PFC_PIN_GROUP(ref_clko),
+ SH_PFC_PIN_GROUP(ext_clki),
+ SH_PFC_PIN_GROUP(lowpwr),
+
+ SH_PFC_PIN_GROUP(jt_sel),
+ SH_PFC_PIN_GROUP(jt_tdo),
+ SH_PFC_PIN_GROUP(jt_tdoen),
+
+ SH_PFC_PIN_GROUP(lcd3_pxclk),
+ SH_PFC_PIN_GROUP(lcd3_pxclkb),
+ SH_PFC_PIN_GROUP(lcd3_clk_i),
+ SH_PFC_PIN_GROUP(lcd3_hs),
+ SH_PFC_PIN_GROUP(lcd3_vs),
+ SH_PFC_PIN_GROUP(lcd3_de),
+ SH_PFC_PIN_GROUP(lcd3_r0),
+ SH_PFC_PIN_GROUP(lcd3_r1),
+ SH_PFC_PIN_GROUP(lcd3_r2),
+ SH_PFC_PIN_GROUP(lcd3_r3),
+ SH_PFC_PIN_GROUP(lcd3_r4),
+ SH_PFC_PIN_GROUP(lcd3_r5),
+ SH_PFC_PIN_GROUP(lcd3_r6),
+ SH_PFC_PIN_GROUP(lcd3_r7),
+ SH_PFC_PIN_GROUP(lcd3_g0),
+ SH_PFC_PIN_GROUP(lcd3_g1),
+ SH_PFC_PIN_GROUP(lcd3_g2),
+ SH_PFC_PIN_GROUP(lcd3_g3),
+ SH_PFC_PIN_GROUP(lcd3_g4),
+ SH_PFC_PIN_GROUP(lcd3_g5),
+ SH_PFC_PIN_GROUP(lcd3_g6),
+ SH_PFC_PIN_GROUP(lcd3_g7),
+ SH_PFC_PIN_GROUP(lcd3_b0),
+ SH_PFC_PIN_GROUP(lcd3_b1),
+ SH_PFC_PIN_GROUP(lcd3_b2),
+ SH_PFC_PIN_GROUP(lcd3_b3),
+ SH_PFC_PIN_GROUP(lcd3_b4),
+ SH_PFC_PIN_GROUP(lcd3_b5),
+ SH_PFC_PIN_GROUP(lcd3_b6),
+ SH_PFC_PIN_GROUP(lcd3_b7),
+
+ SH_PFC_PIN_GROUP(yuv3_clk_o),
+ SH_PFC_PIN_GROUP(yuv3_clk_i),
+ SH_PFC_PIN_GROUP(yuv3_hs),
+ SH_PFC_PIN_GROUP(yuv3_vs),
+ SH_PFC_PIN_GROUP(yuv3_de),
+ SH_PFC_PIN_GROUP(yuv3_d0),
+ SH_PFC_PIN_GROUP(yuv3_d1),
+ SH_PFC_PIN_GROUP(yuv3_d2),
+ SH_PFC_PIN_GROUP(yuv3_d3),
+ SH_PFC_PIN_GROUP(yuv3_d4),
+ SH_PFC_PIN_GROUP(yuv3_d5),
+ SH_PFC_PIN_GROUP(yuv3_d6),
+ SH_PFC_PIN_GROUP(yuv3_d7),
+ SH_PFC_PIN_GROUP(yuv3_d8),
+ SH_PFC_PIN_GROUP(yuv3_d9),
+ SH_PFC_PIN_GROUP(yuv3_d10),
+ SH_PFC_PIN_GROUP(yuv3_d11),
+ SH_PFC_PIN_GROUP(yuv3_d12),
+ SH_PFC_PIN_GROUP(yuv3_d13),
+ SH_PFC_PIN_GROUP(yuv3_d14),
+ SH_PFC_PIN_GROUP(yuv3_d15),
+
+ SH_PFC_PIN_GROUP(tp33_clk),
+ SH_PFC_PIN_GROUP(tp33_ctrl),
+ SH_PFC_PIN_GROUP(tp33_data0),
+ SH_PFC_PIN_GROUP(tp33_data1),
+ SH_PFC_PIN_GROUP(tp33_data2),
+ SH_PFC_PIN_GROUP(tp33_data3),
+ SH_PFC_PIN_GROUP(tp33_data4),
+ SH_PFC_PIN_GROUP(tp33_data5),
+ SH_PFC_PIN_GROUP(tp33_data6),
+ SH_PFC_PIN_GROUP(tp33_data7),
+ SH_PFC_PIN_GROUP(tp33_data8),
+ SH_PFC_PIN_GROUP(tp33_data9),
+ SH_PFC_PIN_GROUP(tp33_data10),
+ SH_PFC_PIN_GROUP(tp33_data11),
+ SH_PFC_PIN_GROUP(tp33_data12),
+ SH_PFC_PIN_GROUP(tp33_data13),
+ SH_PFC_PIN_GROUP(tp33_data14),
+ SH_PFC_PIN_GROUP(tp33_data15),
+
+ SH_PFC_PIN_GROUP(iic0_scl),
+ SH_PFC_PIN_GROUP(iic0_sda),
+
+ SH_PFC_PIN_GROUP(iic1_scl),
+ SH_PFC_PIN_GROUP(iic1_sda),
+
+ SH_PFC_PIN_GROUP(uart1_rx),
+ SH_PFC_PIN_GROUP(uart1_tx),
+ SH_PFC_PIN_GROUP(uart1_ctsb),
+ SH_PFC_PIN_GROUP(uart1_rtsb),
+ SH_PFC_PIN_GROUP(uart2_rx),
+ SH_PFC_PIN_GROUP(uart2_tx),
+ SH_PFC_PIN_GROUP(uart3_rx),
+ SH_PFC_PIN_GROUP(uart3_tx),
+
+ SH_PFC_PIN_GROUP(sd_cki),
+
+ SH_PFC_PIN_GROUP(sdi0_cko),
+ SH_PFC_PIN_GROUP(sdi0_cki),
+ SH_PFC_PIN_GROUP(sdi0_cmd),
+ SH_PFC_PIN_GROUP(sdi0_data0),
+ SH_PFC_PIN_GROUP(sdi0_data1),
+ SH_PFC_PIN_GROUP(sdi0_data2),
+ SH_PFC_PIN_GROUP(sdi0_data3),
+ SH_PFC_PIN_GROUP(sdi0_data4),
+ SH_PFC_PIN_GROUP(sdi0_data5),
+ SH_PFC_PIN_GROUP(sdi0_data6),
+ SH_PFC_PIN_GROUP(sdi0_data7),
+
+ SH_PFC_PIN_GROUP(sdi1_cko),
+ SH_PFC_PIN_GROUP(sdi1_cki),
+ SH_PFC_PIN_GROUP(sdi1_cmd),
+ SH_PFC_PIN_GROUP(sdi1_data0),
+ SH_PFC_PIN_GROUP(sdi1_data1),
+ SH_PFC_PIN_GROUP(sdi1_data2),
+ SH_PFC_PIN_GROUP(sdi1_data3),
+
+ SH_PFC_PIN_GROUP(sdi2_cko),
+ SH_PFC_PIN_GROUP(sdi2_cki),
+ SH_PFC_PIN_GROUP(sdi2_cmd),
+ SH_PFC_PIN_GROUP(sdi2_data0),
+ SH_PFC_PIN_GROUP(sdi2_data1),
+ SH_PFC_PIN_GROUP(sdi2_data2),
+ SH_PFC_PIN_GROUP(sdi2_data3),
+
+ SH_PFC_PIN_GROUP(ab_clk),
+ SH_PFC_PIN_GROUP(ab_csb0),
+ SH_PFC_PIN_GROUP(ab_csb1),
+ SH_PFC_PIN_GROUP(ab_csb2),
+ SH_PFC_PIN_GROUP(ab_csb3),
+ SH_PFC_PIN_GROUP(ab_rdb),
+ SH_PFC_PIN_GROUP(ab_wrb),
+ SH_PFC_PIN_GROUP(ab_wait),
+
+ SH_PFC_PIN_GROUP(ab_adv),
+ SH_PFC_PIN_GROUP(ab_ad0),
+ SH_PFC_PIN_GROUP(ab_ad1),
+ SH_PFC_PIN_GROUP(ab_ad2),
+ SH_PFC_PIN_GROUP(ab_ad3),
+ SH_PFC_PIN_GROUP(ab_ad4),
+ SH_PFC_PIN_GROUP(ab_ad5),
+ SH_PFC_PIN_GROUP(ab_ad6),
+ SH_PFC_PIN_GROUP(ab_ad7),
+ SH_PFC_PIN_GROUP(ab_ad8),
+ SH_PFC_PIN_GROUP(ab_ad9),
+ SH_PFC_PIN_GROUP(ab_ad10),
+ SH_PFC_PIN_GROUP(ab_ad11),
+ SH_PFC_PIN_GROUP(ab_ad12),
+ SH_PFC_PIN_GROUP(ab_ad13),
+ SH_PFC_PIN_GROUP(ab_ad14),
+ SH_PFC_PIN_GROUP(ab_ad15),
+ SH_PFC_PIN_GROUP(ab_a17),
+ SH_PFC_PIN_GROUP(ab_a18),
+ SH_PFC_PIN_GROUP(ab_a19),
+ SH_PFC_PIN_GROUP(ab_a20),
+ SH_PFC_PIN_GROUP(ab_a21),
+ SH_PFC_PIN_GROUP(ab_a22),
+ SH_PFC_PIN_GROUP(ab_a23),
+ SH_PFC_PIN_GROUP(ab_a24),
+ SH_PFC_PIN_GROUP(ab_a25),
+ SH_PFC_PIN_GROUP(ab_a26),
+ SH_PFC_PIN_GROUP(ab_a27),
+ SH_PFC_PIN_GROUP(ab_a28),
+ SH_PFC_PIN_GROUP(ab_ben0),
+ SH_PFC_PIN_GROUP(ab_ben1),
+
+ SH_PFC_PIN_GROUP(dtv_bclk_a),
+ SH_PFC_PIN_GROUP(dtv_psync_a),
+ SH_PFC_PIN_GROUP(dtv_valid_a),
+ SH_PFC_PIN_GROUP(dtv_data_a),
+ SH_PFC_PIN_GROUP(dtv_bclk_b),
+ SH_PFC_PIN_GROUP(dtv_psync_b),
+ SH_PFC_PIN_GROUP(dtv_valid_b),
+ SH_PFC_PIN_GROUP(dtv_data_b),
+
+ SH_PFC_PIN_GROUP(cf_csb0),
+ SH_PFC_PIN_GROUP(cf_csb1),
+ SH_PFC_PIN_GROUP(cf_iordb),
+ SH_PFC_PIN_GROUP(cf_iowrb),
+ SH_PFC_PIN_GROUP(cf_iordy),
+ SH_PFC_PIN_GROUP(cf_reset),
+ SH_PFC_PIN_GROUP(cf_d00),
+ SH_PFC_PIN_GROUP(cf_d01),
+ SH_PFC_PIN_GROUP(cf_d02),
+ SH_PFC_PIN_GROUP(cf_d03),
+ SH_PFC_PIN_GROUP(cf_d04),
+ SH_PFC_PIN_GROUP(cf_d05),
+ SH_PFC_PIN_GROUP(cf_d06),
+ SH_PFC_PIN_GROUP(cf_d07),
+ SH_PFC_PIN_GROUP(cf_d08),
+ SH_PFC_PIN_GROUP(cf_d09),
+ SH_PFC_PIN_GROUP(cf_d10),
+ SH_PFC_PIN_GROUP(cf_d11),
+ SH_PFC_PIN_GROUP(cf_d12),
+ SH_PFC_PIN_GROUP(cf_d13),
+ SH_PFC_PIN_GROUP(cf_d14),
+ SH_PFC_PIN_GROUP(cf_d15),
+ SH_PFC_PIN_GROUP(cf_a00),
+ SH_PFC_PIN_GROUP(cf_a01),
+ SH_PFC_PIN_GROUP(cf_a02),
+ SH_PFC_PIN_GROUP(cf_intrq),
+ SH_PFC_PIN_GROUP(cf_inpackb),
+ SH_PFC_PIN_GROUP(cf_cdb1),
+ SH_PFC_PIN_GROUP(cf_cdb2),
+
+ SH_PFC_PIN_GROUP(usi0_cs1),
+ SH_PFC_PIN_GROUP(usi0_cs2),
+ SH_PFC_PIN_GROUP(usi0_cs3),
+ SH_PFC_PIN_GROUP(usi0_cs4),
+ SH_PFC_PIN_GROUP(usi0_cs5),
+ SH_PFC_PIN_GROUP(usi0_cs6),
+ SH_PFC_PIN_GROUP(usi1_di),
+ SH_PFC_PIN_GROUP(usi1_do),
+
+ SH_PFC_PIN_GROUP(usi2_clk),
+ SH_PFC_PIN_GROUP(usi2_di),
+ SH_PFC_PIN_GROUP(usi2_do),
+ SH_PFC_PIN_GROUP(usi2_cs0),
+ SH_PFC_PIN_GROUP(usi2_cs1),
+ SH_PFC_PIN_GROUP(usi2_cs2),
+
+ SH_PFC_PIN_GROUP(usi3_clk),
+ SH_PFC_PIN_GROUP(usi3_di),
+ SH_PFC_PIN_GROUP(usi3_do),
+ SH_PFC_PIN_GROUP(usi3_cs0),
+
+ SH_PFC_PIN_GROUP(usi4_clk),
+ SH_PFC_PIN_GROUP(usi4_di),
+ SH_PFC_PIN_GROUP(usi4_do),
+ SH_PFC_PIN_GROUP(usi4_cs0),
+ SH_PFC_PIN_GROUP(usi4_cs1),
+
+ SH_PFC_PIN_GROUP(usi5_clk_a),
+ SH_PFC_PIN_GROUP(usi5_di_a),
+ SH_PFC_PIN_GROUP(usi5_do_a),
+ SH_PFC_PIN_GROUP(usi5_cs0_a),
+ SH_PFC_PIN_GROUP(usi5_cs1_a),
+ SH_PFC_PIN_GROUP(usi5_cs2_a),
+ SH_PFC_PIN_GROUP(usi5_clk_b),
+ SH_PFC_PIN_GROUP(usi5_di_b),
+ SH_PFC_PIN_GROUP(usi5_do_b),
+ SH_PFC_PIN_GROUP(usi5_cs0_b),
+ SH_PFC_PIN_GROUP(usi5_cs1_b),
+ SH_PFC_PIN_GROUP(usi5_cs2_b),
+ SH_PFC_PIN_GROUP(usi5_cs3_b),
+ SH_PFC_PIN_GROUP(usi5_cs4_b),
+
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm1),
+
+ SH_PFC_PIN_GROUP(ntsc_clk),
+ SH_PFC_PIN_GROUP(ntsc_data0),
+ SH_PFC_PIN_GROUP(ntsc_data1),
+ SH_PFC_PIN_GROUP(ntsc_data2),
+ SH_PFC_PIN_GROUP(ntsc_data3),
+ SH_PFC_PIN_GROUP(ntsc_data4),
+ SH_PFC_PIN_GROUP(ntsc_data5),
+ SH_PFC_PIN_GROUP(ntsc_data6),
+ SH_PFC_PIN_GROUP(ntsc_data7),
+
+ SH_PFC_PIN_GROUP(cam_clko),
+ SH_PFC_PIN_GROUP(cam_clki),
+ SH_PFC_PIN_GROUP(cam_vs),
+ SH_PFC_PIN_GROUP(cam_hs),
+ SH_PFC_PIN_GROUP(cam_yuv0),
+ SH_PFC_PIN_GROUP(cam_yuv1),
+ SH_PFC_PIN_GROUP(cam_yuv2),
+ SH_PFC_PIN_GROUP(cam_yuv3),
+ SH_PFC_PIN_GROUP(cam_yuv4),
+ SH_PFC_PIN_GROUP(cam_yuv5),
+ SH_PFC_PIN_GROUP(cam_yuv6),
+ SH_PFC_PIN_GROUP(cam_yuv7),
+
+ SH_PFC_PIN_GROUP(hsi_cawake),
+ SH_PFC_PIN_GROUP(hsi_cadata),
+ SH_PFC_PIN_GROUP(hsi_caflag),
+ SH_PFC_PIN_GROUP(hsi_acready),
+ SH_PFC_PIN_GROUP(hsi_acwake),
+ SH_PFC_PIN_GROUP(hsi_acdata),
+ SH_PFC_PIN_GROUP(hsi_acflag),
+ SH_PFC_PIN_GROUP(hsi_caready),
+
+ SH_PFC_PIN_GROUP(usb_vbus),
+};
+
+static const char * const jtag_groups[] = {
+ "jt_sel",
+ "jt_tdo",
+ "jt_tdoen",
+};
+
+static const char * const lcd_groups[] = {
+ "lcd3_pxclk",
+ "lcd3_pxclkb",
+ "lcd3_clk_i",
+ "lcd3_hs",
+ "lcd3_vs",
+ "lcd3_de",
+ "lcd3_r0",
+ "lcd3_r1",
+ "lcd3_r2",
+ "lcd3_r3",
+ "lcd3_r4",
+ "lcd3_r5",
+ "lcd3_r6",
+ "lcd3_r7",
+ "lcd3_g0",
+ "lcd3_g1",
+ "lcd3_g2",
+ "lcd3_g3",
+ "lcd3_g4",
+ "lcd3_g5",
+ "lcd3_g6",
+ "lcd3_g7",
+ "lcd3_b0",
+ "lcd3_b1",
+ "lcd3_b2",
+ "lcd3_b3",
+ "lcd3_b4",
+ "lcd3_b5",
+ "lcd3_b6",
+ "lcd3_b7",
+};
+
+static const char * const yuv_groups[] = {
+ "yuv3_clk_o",
+ "yuv3_clk_i",
+ "yuv3_hs",
+ "yuv3_vs",
+ "yuv3_de",
+ "yuv3_d0",
+ "yuv3_d1",
+ "yuv3_d2",
+ "yuv3_d3",
+ "yuv3_d4",
+ "yuv3_d5",
+ "yuv3_d6",
+ "yuv3_d7",
+ "yuv3_d8",
+ "yuv3_d9",
+ "yuv3_d10",
+ "yuv3_d11",
+ "yuv3_d12",
+ "yuv3_d13",
+ "yuv3_d14",
+ "yuv3_d15",
+};
+
+static const char * const tp33_groups[] = {
+ "tp33_clk",
+ "tp33_ctrl",
+ "tp33_data0",
+ "tp33_data1",
+ "tp33_data2",
+ "tp33_data3",
+ "tp33_data4",
+ "tp33_data5",
+ "tp33_data6",
+ "tp33_data7",
+ "tp33_data8",
+ "tp33_data9",
+ "tp33_data10",
+ "tp33_data11",
+ "tp33_data12",
+ "tp33_data13",
+ "tp33_data14",
+ "tp33_data15",
+};
+
+static const char * const iic0_groups[] = {
+ "iic0_scl",
+ "iic0_sda",
+};
+
+static const char * const iic1_groups[] = {
+ "iic1_scl",
+ "iic1_sda",
+};
+
+static const char * const uart1_groups[] = {
+ "uart1_rx",
+ "uart1_tx",
+ "uart1_ctsb",
+ "uart1_rtsb",
+};
+
+static const char * const uart2_groups[] = {
+ "uart2_rx",
+ "uart2_tx",
+};
+
+static const char * const uart3_groups[] = {
+ "uart3_rx",
+ "uart3_tx",
+};
+
+static const char * const sd_groups[] = {
+ "sd_cki",
+};
+
+static const char * const sdi0_groups[] = {
+ "sdi0_cko",
+ "sdi0_cki",
+ "sdi0_cmd",
+ "sdi0_data0",
+ "sdi0_data1",
+ "sdi0_data2",
+ "sdi0_data3",
+ "sdi0_data4",
+ "sdi0_data5",
+ "sdi0_data6",
+ "sdi0_data7",
+};
+
+static const char * const sdi1_groups[] = {
+ "sdi1_cko",
+ "sdi1_cki",
+ "sdi1_cmd",
+ "sdi1_data0",
+ "sdi1_data1",
+ "sdi1_data2",
+ "sdi1_data3",
+};
+
+static const char * const sdi2_groups[] = {
+ "sdi2_cko",
+ "sdi2_cki",
+ "sdi2_cmd",
+ "sdi2_data0",
+ "sdi2_data1",
+ "sdi2_data2",
+ "sdi2_data3",
+};
+
+static const char * const ab_groups[] = {
+ "ab_clk",
+ "ab_csb0",
+ "ab_csb1",
+ "ab_csb2",
+ "ab_csb3",
+ "ab_rdb",
+ "ab_wrb",
+ "ab_wait",
+ "ab_adv",
+ "ab_ad0",
+ "ab_ad1",
+ "ab_ad2",
+ "ab_ad3",
+ "ab_ad4",
+ "ab_ad5",
+ "ab_ad6",
+ "ab_ad7",
+ "ab_ad8",
+ "ab_ad9",
+ "ab_ad10",
+ "ab_ad11",
+ "ab_ad12",
+ "ab_ad13",
+ "ab_ad14",
+ "ab_ad15",
+ "ab_a17",
+ "ab_a18",
+ "ab_a19",
+ "ab_a20",
+ "ab_a21",
+ "ab_a22",
+ "ab_a23",
+ "ab_a24",
+ "ab_a25",
+ "ab_a26",
+ "ab_a27",
+ "ab_a28",
+ "ab_ben0",
+ "ab_ben1",
+};
+
+static const char * const dtv_groups[] = {
+ "dtv_bclk_a",
+ "dtv_psync_a",
+ "dtv_valid_a",
+ "dtv_data_a",
+ "dtv_bclk_b",
+ "dtv_psync_b",
+ "dtv_valid_b",
+ "dtv_data_b",
+};
+
+static const char * const cf_groups[] = {
+ "cf_csb0",
+ "cf_csb1",
+ "cf_iordb",
+ "cf_iowrb",
+ "cf_iordy",
+ "cf_reset",
+ "cf_d00",
+ "cf_d01",
+ "cf_d02",
+ "cf_d03",
+ "cf_d04",
+ "cf_d05",
+ "cf_d06",
+ "cf_d07",
+ "cf_d08",
+ "cf_d09",
+ "cf_d10",
+ "cf_d11",
+ "cf_d12",
+ "cf_d13",
+ "cf_d14",
+ "cf_d15",
+ "cf_a00",
+ "cf_a01",
+ "cf_a02",
+ "cf_intrq",
+ "cf_inpackb",
+ "cf_cdb1",
+ "cf_cdb2",
+};
+
+static const char * const usi0_groups[] = {
+ "usi0_cs1",
+ "usi0_cs2",
+ "usi0_cs3",
+ "usi0_cs4",
+ "usi0_cs5",
+ "usi0_cs6",
+};
+
+static const char * const usi1_groups[] = {
+ "usi1_di",
+ "usi1_do",
+};
+
+static const char * const usi2_groups[] = {
+ "usi2_clk",
+ "usi2_di",
+ "usi2_do",
+ "usi2_cs0",
+ "usi2_cs1",
+ "usi2_cs2",
+};
+
+static const char * const usi3_groups[] = {
+ "usi3_clk",
+ "usi3_di",
+ "usi3_do",
+ "usi3_cs0",
+};
+
+static const char * const usi4_groups[] = {
+ "usi4_clk",
+ "usi4_di",
+ "usi4_do",
+ "usi4_cs0",
+ "usi4_cs1",
+};
+
+
+static const char * const usi5_groups[] = {
+ "usi5_clk_a",
+ "usi5_di_a",
+ "usi5_do_a",
+ "usi5_cs0_a",
+ "usi5_cs1_a",
+ "usi5_cs2_a",
+ "usi5_clk_b",
+ "usi5_di_b",
+ "usi5_do_b",
+ "usi5_cs0_b",
+ "usi5_cs1_b",
+ "usi5_cs2_b",
+ "usi5_cs3_b",
+ "usi5_cs4_b",
+};
+
+static const char * const pwm_groups[] = {
+ "pwm0",
+ "pwm1",
+};
+
+static const char * const ntsc_groups[] = {
+ "ntsc_clk",
+ "ntsc_data0",
+ "ntsc_data1",
+ "ntsc_data2",
+ "ntsc_data3",
+ "ntsc_data4",
+ "ntsc_data5",
+ "ntsc_data6",
+ "ntsc_data7",
+};
+
+static const char * const cam_groups[] = {
+ "cam_clko",
+ "cam_clki",
+ "cam_vs",
+ "cam_hs",
+ "cam_yuv0",
+ "cam_yuv1",
+ "cam_yuv2",
+ "cam_yuv3",
+ "cam_yuv4",
+ "cam_yuv5",
+ "cam_yuv6",
+ "cam_yuv7",
+};
+
+static const char * const hsi_groups[] = {
+ "hsi_cawake",
+ "hsi_cadata",
+ "hsi_caflag",
+ "hsi_acready",
+ "hsi_acwake",
+ "hsi_acdata",
+ "hsi_acflag",
+ "hsi_caready",
+};
+
+static const char * const usb_groups[] = {
+ "usb_vbus",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(jtag),
+ SH_PFC_FUNCTION(lcd),
+ SH_PFC_FUNCTION(yuv),
+ SH_PFC_FUNCTION(tp33),
+ SH_PFC_FUNCTION(iic0),
+ SH_PFC_FUNCTION(iic1),
+ SH_PFC_FUNCTION(uart1),
+ SH_PFC_FUNCTION(uart2),
+ SH_PFC_FUNCTION(uart3),
+ SH_PFC_FUNCTION(sd),
+ SH_PFC_FUNCTION(sdi0),
+ SH_PFC_FUNCTION(sdi1),
+ SH_PFC_FUNCTION(sdi2),
+ SH_PFC_FUNCTION(ab),
+ SH_PFC_FUNCTION(dtv),
+ SH_PFC_FUNCTION(cf),
+ SH_PFC_FUNCTION(usi0),
+ SH_PFC_FUNCTION(usi1),
+ SH_PFC_FUNCTION(usi2),
+ SH_PFC_FUNCTION(usi3),
+ SH_PFC_FUNCTION(usi4),
+ SH_PFC_FUNCTION(usi5),
+ SH_PFC_FUNCTION(ntsc),
+ SH_PFC_FUNCTION(cam),
+ SH_PFC_FUNCTION(hsi),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) {
+ 0, GP_0_31_FN, /* GP: 031 PIN: J18 */
+ 0, GP_0_30_FN, /* GP: 030 PIN: H18 */
+ 0, GP_0_29_FN, /* GP: 029 PIN: G18 */
+ 0, GP_0_28_FN, /* GP: 028 PIN: F18 */
+ 0, GP_0_27_FN, /* GP: 027 PIN: F17 */
+ 0, GP_0_26_FN, /* GP: 026 PIN: F16 */
+ 0, GP_0_25_FN, /* GP: 025 PIN: E20 */
+ 0, GP_0_24_FN, /* GP: 024 PIN: D20 */
+ FN_LCD3_1_0_GP_0_23, GP_0_23_FN, /* GP: 023 PIN: D19 */
+ FN_LCD3_1_0_GP_0_22, GP_0_22_FN, /* GP: 022 PIN: C20 */
+ FN_LCD3_1_0_GP_0_21, GP_0_21_FN, /* GP: 021 PIN: B21 */
+ FN_LCD3_1_0_GP_0_20, GP_0_20_FN, /* GP: 020 PIN: A21 */
+ FN_LCD3_PXCLKB, GP_0_19_FN, /* GP: 019 PIN: C21 */
+ FN_LCD3_1_0_GP_0_18, GP_0_18_FN, /* GP: 018 PIN: B22 */
+ 0, GP_0_17_FN, /* GP: 017 PIN: W20 */
+ 0, GP_0_16_FN, /* GP: 016 PIN: W21 */
+ 0, GP_0_15_FN, /* GP: 015 PIN: Y19 */
+ 0, GP_0_14_FN, /* GP: 014 PIN: Y20 */
+ 0, GP_0_13_FN, /* GP: 013 PIN: Y21 */
+ 0, GP_0_12_FN, /* GP: 012 PIN: AA20 */
+ 0, GP_0_11_FN, /* GP: 011 PIN: AA21 */
+ 0, GP_0_10_FN, /* GP: 010 PIN: AA22 */
+ 0, GP_0_9_FN, /* GP: 009 PIN: V15 */
+ 0, GP_0_8_FN, /* GP: 008 PIN: V16 */
+ 0, GP_0_7_FN, /* GP: 007 PIN: V17 */
+ 0, GP_0_6_FN, /* GP: 006 PIN: V18 */
+ FN_EXT_CLKI, GP_0_5_FN, /* GP: 005 PIN: U8 */
+ FN_REF_CLKO, GP_0_4_FN, /* GP: 004 PIN: V8 */
+ FN_ERR_RST_REQB, GP_0_3_FN, /* GP: 003 PIN: U9 */
+ FN_JT_SEL, GP_0_2_FN, /* GP: 002 PIN: V9 */
+ 0, GP_0_1_FN, /* GP: 001 PIN: U10 */
+ 0, GP_0_0_FN, /* GP: 000 PIN: V10 */
+ }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) {
+ FN_SDI1_CMD, GP_1_31_FN, /* GP: 063 PIN: AC21 */
+ FN_SDI1_CKI, GP_1_30_FN, /* GP: 062 PIN: AA23 */
+ FN_SDI1_CKO, GP_1_29_FN, /* GP: 061 PIN: AB22 */
+ FN_SDI0_DATA7, GP_1_28_FN, /* GP: 060 PIN: Y16 */
+ FN_SDI0_DATA6, GP_1_27_FN, /* GP: 059 PIN: AA16 */
+ FN_SDI0_DATA5, GP_1_26_FN, /* GP: 058 PIN: Y15 */
+ FN_SDI0_DATA4, GP_1_25_FN, /* GP: 057 PIN: AA15 */
+ FN_SDI0_DATA3, GP_1_24_FN, /* GP: 056 PIN: Y14 */
+ FN_SDI0_DATA2, GP_1_23_FN, /* GP: 055 PIN: AA14 */
+ FN_SDI0_DATA1, GP_1_22_FN, /* GP: 054 PIN: Y13 */
+ FN_SDI0_DATA0, GP_1_21_FN, /* GP: 053 PIN: AA13 */
+ FN_SDI0_CMD, GP_1_20_FN, /* GP: 052 PIN: Y12 */
+ FN_SDI0_CKI, GP_1_19_FN, /* GP: 051 PIN: AC18 */
+ FN_SDI0_CKO, GP_1_18_FN, /* GP: 050 PIN: AB18 */
+ 0, GP_1_17_FN, /* GP: 049 PIN: AB16 */
+ FN_SD_CKI, GP_1_16_FN, /* GP: 048 PIN: AC19 */
+ FN_IIC_1_0_GP_1_15, GP_1_15_FN, /* GP: 047 PIN: Y8 */
+ FN_IIC_1_0_GP_1_14, GP_1_14_FN, /* GP: 046 PIN: Y9 */
+ FN_IIC0_SDA, GP_1_13_FN, /* GP: 045 PIN: AA8 */
+ FN_IIC0_SCL, GP_1_12_FN, /* GP: 044 PIN: AA9 */
+ FN_LCD3_11_10_GP_1_11, GP_1_11_FN, /* GP: 043 PIN: A15 */
+ FN_LCD3_11_10_GP_1_10, GP_1_10_FN, /* GP: 042 PIN: A16 */
+ FN_LCD3_11_10_GP_1_9, GP_1_9_FN, /* GP: 041 PIN: A17 */
+ FN_LCD3_11_10_GP_1_8, GP_1_8_FN, /* GP: 040 PIN: A18 */
+ FN_LCD3_9_8_GP_1_7, GP_1_7_FN, /* GP: 039 PIN: D18 */
+ FN_LCD3_9_8_GP_1_6, GP_1_6_FN, /* GP: 038 PIN: C18 */
+ FN_LCD3_R5, GP_1_5_FN, /* GP: 037 PIN: B18 */
+ FN_LCD3_R4, GP_1_4_FN, /* GP: 036 PIN: C19 */
+ FN_LCD3_R3, GP_1_3_FN, /* GP: 035 PIN: B19 */
+ FN_LCD3_R2, GP_1_2_FN, /* GP: 034 PIN: A19 */
+ FN_LCD3_R1, GP_1_1_FN, /* GP: 033 PIN: B20 */
+ FN_LCD3_R0, GP_1_0_FN, /* GP: 032 PIN: A20 */
+ }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) {
+ FN_AB_1_0_GP_2_31, GP_2_31_FN, /* GP: 095 PIN: L21 */
+ FN_AB_1_0_GP_2_30, GP_2_30_FN, /* GP: 094 PIN: K21 */
+ FN_AB_1_0_GP_2_29, GP_2_29_FN, /* GP: 093 PIN: J21 */
+ FN_AB_7_6_GP_2_28, GP_2_28_FN, /* GP: 092 PIN: J22 */
+ FN_AB_7_6_GP_2_27, GP_2_27_FN, /* GP: 091 PIN: H21 */
+ FN_AB_5_4_GP_2_26, GP_2_26_FN, /* GP: 090 PIN: H22 */
+ FN_AB_5_4_GP_2_25, GP_2_25_FN, /* GP: 089 PIN: H23 */
+ FN_AB_3_2_GP_2_24, GP_2_24_FN, /* GP: 088 PIN: G21 */
+ FN_AB_3_2_GP_2_23, GP_2_23_FN, /* GP: 087 PIN: G22 */
+ FN_AB_3_2_GP_2_22, GP_2_22_FN, /* GP: 086 PIN: G23 */
+ FN_AB_3_2_GP_2_21, GP_2_21_FN, /* GP: 085 PIN: F21 */
+ FN_AB_1_0_GP_2_20, GP_2_20_FN, /* GP: 084 PIN: F22 */
+ FN_AB_1_0_GP_2_19, GP_2_19_FN, /* GP: 083 PIN: F23 */
+ FN_AB_1_0_GP_2_18, GP_2_18_FN, /* GP: 082 PIN: E22 */
+ FN_AB_1_0_GP_2_17, GP_2_17_FN, /* GP: 081 PIN: E23 */
+ FN_AB_1_0_GP_2_16, GP_2_16_FN, /* GP: 080 PIN: D22 */
+ FN_AB_1_0_GP_2_15, GP_2_15_FN, /* GP: 079 PIN: D23 */
+ FN_AB_1_0_GP_2_14, GP_2_14_FN, /* GP: 078 PIN: C22 */
+ FN_AB_1_0_GP_2_13, GP_2_13_FN, /* GP: 077 PIN: C23 */
+ FN_AB_1_0_GP_2_12, GP_2_12_FN, /* GP: 076 PIN: K20 */
+ FN_AB_1_0_GP_2_11, GP_2_11_FN, /* GP: 075 PIN: L20 */
+ FN_AB_1_0_GP_2_10, GP_2_10_FN, /* GP: 074 PIN: H20 */
+ FN_AB_1_0_GP_2_9, GP_2_9_FN, /* GP: 073 PIN: J20 */
+ FN_AB_1_0_GP_2_8, GP_2_8_FN, /* GP: 072 PIN: G20 */
+ FN_AB_1_0_GP_2_7, GP_2_7_FN, /* GP: 071 PIN: F20 */
+ FN_AB_CSB1, GP_2_6_FN, /* GP: 070 PIN: E21 */
+ FN_AB_CSB0, GP_2_5_FN, /* GP: 069 PIN: D21 */
+ FN_AB_CLK, GP_2_4_FN, /* GP: 068 PIN: J23 */
+ FN_SDI1_DATA3, GP_2_3_FN, /* GP: 067 PIN: AA19 */
+ FN_SDI1_DATA2, GP_2_2_FN, /* GP: 066 PIN: AB19 */
+ FN_SDI1_DATA1, GP_2_1_FN, /* GP: 065 PIN: AB20 */
+ FN_SDI1_DATA0, GP_2_0_FN, /* GP: 064 PIN: AB21 */
+ }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) {
+ FN_NTSC_DATA4, GP_3_31_FN, /* GP: 127 PIN: T20 */
+ FN_NTSC_DATA3, GP_3_30_FN, /* GP: 126 PIN: R18 */
+ FN_NTSC_DATA2, GP_3_29_FN, /* GP: 125 PIN: R20 */
+ FN_NTSC_DATA1, GP_3_28_FN, /* GP: 124 PIN: P18 */
+ FN_NTSC_DATA0, GP_3_27_FN, /* GP: 123 PIN: P20 */
+ FN_NTSC_CLK, GP_3_26_FN, /* GP: 122 PIN: V20 */
+ FN_USI_9_8_GP_3_21, GP_3_25_FN, /* GP: 121 PIN: Y5 */
+ FN_USI_9_8_GP_3_20, GP_3_24_FN, /* GP: 120 PIN: AA4 */
+ FN_USI_7_6_GP_3_19, GP_3_23_FN, /* GP: 119 PIN: AB3 */
+ FN_USI_5_4_GP_3_18, GP_3_22_FN, /* GP: 118 PIN: AB4 */
+ FN_USI_5_4_GP_3_17, GP_3_21_FN, /* GP: 117 PIN: AC3 */
+ FN_USI_5_4_GP_3_16, GP_3_20_FN, /* GP: 116 PIN: AC4 */
+ FN_USI_5_4_GP_3_15, GP_3_19_FN, /* GP: 115 PIN: AC5 */
+ FN_USI_3_2_GP_3_14, GP_3_18_FN, /* GP: 114 PIN: Y6 */
+ FN_USI_3_2_GP_3_13, GP_3_17_FN, /* GP: 113 PIN: AA7 */
+ FN_USI_1_0_GP_3_12, GP_3_16_FN, /* GP: 112 PIN: Y7 */
+ FN_USI_1_0_GP_3_11, GP_3_15_FN, /* GP: 111 PIN: AA5 */
+ FN_USI_1_0_GP_3_10, GP_3_14_FN, /* GP: 110 PIN: AA6 */
+ FN_USI_1_0_GP_3_9, GP_3_13_FN, /* GP: 109 PIN: AB5 */
+ FN_USI1_DO, GP_3_12_FN, /* GP: 108 PIN: D10 */
+ FN_USI1_DI, GP_3_11_FN, /* GP: 107 PIN: C10 */
+ FN_USI0_CS2, GP_3_10_FN, /* GP: 106 PIN: B9 */
+ FN_USI0_CS1, GP_3_9_FN, /* GP: 105 PIN: B8 */
+ FN_AB_13_12_GP_3_8, GP_3_8_FN, /* GP: 104 PIN: M17 */
+ FN_AB_13_12_GP_3_7, GP_3_7_FN, /* GP: 103 PIN: L17 */
+ FN_AB_11_10_GP_3_6, GP_3_6_FN, /* GP: 102 PIN: N18 */
+ FN_AB_11_10_GP_3_5, GP_3_5_FN, /* GP: 101 PIN: M18 */
+ FN_AB_11_10_GP_3_4, GP_3_4_FN, /* GP: 100 PIN: L18 */
+ FN_AB_9_8_GP_3_3, GP_3_3_FN, /* GP: 099 PIN: N20 */
+ FN_AB_9_8_GP_3_2, GP_3_2_FN, /* GP: 098 PIN: M20 */
+ FN_AB_9_8_GP_3_1, GP_3_1_FN, /* GP: 097 PIN: N21 */
+ FN_AB_A20, GP_3_0_FN, /* GP: 096 PIN: M21 */
+ }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) {
+ 0, 0,
+ FN_UART_1_0_GP_4_30, GP_4_30_FN, /* GP: 158 PIN: AB10 */
+ FN_UART_1_0_GP_4_29, GP_4_29_FN, /* GP: 157 PIN: AA10 */
+ FN_UART1_TX, GP_4_28_FN, /* GP: 156 PIN: Y10 */
+ FN_UART1_RX, GP_4_27_FN, /* GP: 155 PIN: Y11 */
+ FN_LOWPWR, GP_4_26_FN, /* GP: 154 PIN: A12 */
+ FN_USB_VBUS, GP_4_25_FN, /* GP: 153 PIN: AA12 */
+ FN_JT_TDOEN, GP_4_24_FN, /* GP: 152 PIN: F13 */
+ FN_JT_TDO, GP_4_23_FN, /* GP: 151 PIN: D13 */
+ FN_HSI_1_0_GP_4_22, GP_4_22_FN, /* GP: 150 PIN: M22 */
+ FN_HSI_1_0_GP_4_21, GP_4_21_FN, /* GP: 149 PIN: M23 */
+ FN_HSI_1_0_GP_4_20, GP_4_20_FN, /* GP: 148 PIN: N23 */
+ FN_HSI_1_0_GP_4_19, GP_4_19_FN, /* GP: 147 PIN: N22 */
+ FN_HSI_1_0_GP_4_18, GP_4_18_FN, /* GP: 146 PIN: L22 */
+ FN_HSI_1_0_GP_4_17, GP_4_17_FN, /* GP: 145 PIN: L23 */
+ FN_HSI_1_0_GP_4_16, GP_4_16_FN, /* GP: 144 PIN: K23 */
+ FN_HSI_1_0_GP_4_15, GP_4_15_FN, /* GP: 143 PIN: K22 */
+ FN_CAM_YUV7, GP_4_14_FN, /* GP: 142 PIN: V23 */
+ FN_CAM_YUV6, GP_4_13_FN, /* GP: 141 PIN: V22 */
+ FN_CAM_YUV5, GP_4_12_FN, /* GP: 140 PIN: U23 */
+ FN_CAM_YUV4, GP_4_11_FN, /* GP: 139 PIN: U22 */
+ FN_CAM_YUV3, GP_4_10_FN, /* GP: 138 PIN: U21 */
+ FN_CAM_YUV2, GP_4_9_FN, /* GP: 137 PIN: T23 */
+ FN_CAM_YUV1, GP_4_8_FN, /* GP: 136 PIN: T22 */
+ FN_CAM_YUV0, GP_4_7_FN, /* GP: 135 PIN: T21 */
+ FN_CAM_HS, GP_4_6_FN, /* GP: 134 PIN: V21 */
+ FN_CAM_VS, GP_4_5_FN, /* GP: 133 PIN: W22 */
+ FN_CAM_CLKI, GP_4_4_FN, /* GP: 132 PIN: Y23 */
+ FN_CAM_CLKO, GP_4_3_FN, /* GP: 131 PIN: W23 */
+ FN_NTSC_DATA7, GP_4_2_FN, /* GP: 130 PIN: U18 */
+ FN_NTSC_DATA6, GP_4_1_FN, /* GP: 129 PIN: U20 */
+ FN_NTSC_DATA5, GP_4_0_FN, /* GP: 128 PIN: T18 */
+ }
+ },
+ { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 2, 2, 2, 2, 2, 2) {
+ /* 31 - 12 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 11 - 10 */
+ FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
+ FN_SEL_LCD3_11_10_10, 0,
+ /* 9 - 8 */
+ FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
+ /* 7 - 2 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 1 - 0 */
+ FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
+ /* 31 - 2 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 1 - 0 */
+ FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
+ /* 31 - 2 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 1 - 0 */
+ FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2) {
+ /* 31 - 14 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ /* 13 - 12 */
+ FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
+ /* 11 - 10 */
+ FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0,
+ /* 9 - 8 */
+ FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0,
+ /* 7 - 6 */
+ FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0,
+ /* 5 - 4 */
+ FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01,
+ FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11,
+ /* 3 - 2 */
+ FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01,
+ FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
+ /* 1 - 0 */
+ FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
+ }
+ },
+ { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) {
+ /* 31 - 10 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 9 - 8 */
+ FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
+ /* 7 - 6 */
+ FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0,
+ /* 5 - 4 */
+ FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0,
+ /* 3 - 2 */
+ FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
+ /* 1 - 0 */
+ FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
+ /* 31 - 2 */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /* 1 - 0 */
+ FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
+ }
+ },
+ { },
+};
+
+const struct sh_pfc_soc_info emev2_pinmux_info = {
+ .name = "emev2_pfc",
+
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+
+ .gpio_data = pinmux_data,
+ .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
--
2.1.3
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