Re: DRAM unreliable under specific access patern

[Andy Lutomirski]

On Wed, Dec 24, 2014 at 8:38 AM, Pavel Machek <pavel@xxxxxx> wrote:
> Hi!
>
> It seems that it is easy to induce DRAM bit errors by doing repeated
> reads from adjacent memory cells on common hw. Details are at
>
> https://www.ece.cmu.edu/~safari/pubs/kim-isca14.pdf
>
> . Older memory modules seem to work better, and ECC should detect
> this. Paper has inner loop that should trigger this.
>
> Workarounds seem to be at hardware level, and tricky, too.

One mostly-effective solution would be to stop buying computers
without ECC.  Unfortunately, no one seems to sell non-server chips
that can do ECC.

>
> Does anyone have implementation of detector? Any ideas how to work
> around it in software?
>

Platform-dependent page coloring with very strict, and impossible to
implement fully correctly, page allocation constraints?

--Andy

>                                                                         Pavel
> --
> (english) http://www.livejournal.com/~pavelmachek
> (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html



-- 
Andy Lutomirski
AMA Capital Management, LLC
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